Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SMBus 2.0 Unit 2 - PECI—C2000 Product Family
CPU Thermal and Power Optimization Capabilities
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
424
Order Number: 330061-002US
17.9.12
Package Power Limits For Multiple Turbo Modes (Index = 26
and 27)
This feature allows the PECI host to program two power limit values to support multiple
turbo modes. The operating systems and drivers can balance the power budget using
these two limits. Two separate PECI requests are available to program the lower and
upper 32 bits of the power limit data shown in
The units for the Power Limit and Control Time Window are determined as per the
Package Power SKU Unit settings described in
, while the valid range for power limit values are
determined by the Package Power SKU settings described in
.
Setting the Clamp Mode bits is required to allow the cores to go into power states
below what the operating system originally requested. The Power Limit Enable bits
should be set to enable the power limiting function. Power Limit values, enable and
clamp mode bits can all be set in the same command cycle.
Intel recommends exclusive use of just one entity or interface, PECI for instance, to
manage all processor package power limiting and budgeting needs. If PECI is being
used to manage package power limiting activities, BIOS should lock out all subsequent
in-band package power limiting accesses by setting bit 31 of the
MSR_PKG_POWER_LIMIT (MSR 610h) or PKG_TURBO_POWER_LIMIT (SoC sideband
Port 04h, offset 7 and 8) register to 1.
Power Limit #1 is intended to limit processor power consumption to any reasonable
value below TDP and defaults to TDP. Power Limit #1 values may be impacted by the
processor heat sinks and system air flow. Processor Power Limit #2 can be used as
appropriate to limit the current drawn by the processor to prevent any external power
supply unit issues.
Power Limit #2 should always be programmed to a value (typically 20%) higher than
Power Limit #1 and has no default value associated with it.
Though this feature is disabled by default and external programming is required to
enable, initialize and control Package Power Limit values and time windows, the
processor package will still turbo to TDP if Power Limit #1 is not enabled or initialized.
Figure 17-24.Package Turbo Power Limit Data
Power Limit #2
32
63
Control Time
Window #2
48
56
46
47
Power Limit Enable #2
55
Reserved
Clamp Mode #2
Power Limit #1
0
31
Control Time
Window #1
24
Power Limit Enable #1
23
Reserved
Clamp Mode #1
49
16
14
15
17