Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

487

All commands other than the standard (memory) reads must be programmed by the 

software in the Software Sequencing Control, Flash Address, Flash Data, and Opcode 

Configuration registers. The software must issue either Read ID or Read JEDEC ID, or a 

combination of the two to determine what Flash component is attached. Based on the 

Read ID, the software determines the appropriate opcode instruction sets to set in the 

program registers and at what SPI frequency to run the command.

The software must program the flash linear address for all commands, even for those 

commands that do not require an address such as the Read ID or Read Status. This is 

because the SPI controller uses the address to determine which chip select to use.

The opcode type and data byte count fields determine how many clocks to run before 

deasserting the chip enable. The Flash data is always shifted in for the number of bytes 

specified and the Flash data out is always shifted out for the number of data bytes 

specified. 

The hardware restricts the burst lengths that are allowed.

A status bit indicates when the cycle has completed on the SPI port allowing the host to 

know when read results are checked and/or when to initiate a new command.

The controller also provides the atomic cycle sequence for performing erases and writes 

to the SPI Flash. When this bit is 1 (and the Go bit is written to 1), a sequence of cycles 

is performed on the SPI interface without allowing other SPI devices to arbitrate and 

interleave cycles to the Flash device. In this case, the specified cycle is preceded by the 

Prefix command (8-bit programmable opcode) and followed by repeated reads to the 

Status Register (opcode 05h) until bit 0 indicates the cycle has completed. The 

hardware does not attempt to check that the programmed cycle is a write or erase.

If a programmed access is initiated (Cycle Go written to 1) while the SPI controller is 

already busy with a direct memory read, then the SPI host hardware holds the new 

programmed access pending until the preceding SPI access completes. 

Once the SPI controller has committed to running a programmed access, subsequent 

writes to the programmed cycle registers that occur before it has completed do not 

modify the original transaction and result in the assertion of the FCERR bit. The 

software never purposely behaves in this way and relies on this behavior. However, the 

FCERR bit provides basic error reporting in this situation. Writes to the following 

registers cause the FCERR bit assertion in this situation:

• Software Sequencing Control register
• Software Sequencing Address register
• SPI Data register

With the exception of illegal opcodes, the SPI controller does not police which opcodes 

are valid to be used in software sequencing. For example, if the software programs a 

dual-output fast read opcode, then the dual-output fast read cycle is issued, 

independent of whether the Dual-Output Fast Read Enable bit was set in the 

component descriptor section.