Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

518

Order Number: 330061-002US

Not all of the Customer GPIOs have the edge-detect capability. The following do have 

this capability:

• GPIOS[7:0]
• GPIO_SUS[3:0] and GPIO_SUS[7:6]

When programmed to be used as a Customer GPIO (the SC_USE_SEL/SUS_USE_SEL 

register bit is 1 for the SC/SUS GPIO), the GPIO supports General-Purpose Input (GPI) 

edge-triggered events. All GPIO input pins are individually configured by the software 

to generate a System Management Interrupt (SMI) or System Control Interrupt (SCI). 

The Customer GPIOs do not have the capabilities to generate IRQ interrupts.

These Customer GPIO input pins are setup to for positive- or negative-edge detection 

to indicate the event. This is done by programming the GP_TPE and GPE_TNE registers. 

When the GPI edge event is detected, the SoC sends the appropriate SMI or SCI 

message to the CPU.

Besides setting the corresponding bit to 1 of the SC_USE_SEL/SUS_USE_SEL register, 

the polarity of the GPI event is configured in the SC_TPE/SUS_TPE and SC_TNE/

SUS_TPE registers.

Refer to the GPE0a_EN - General Purpose Event 0 Enables (GPE0a_EN)—Offset 28h, 

ALT_GPIO_SMI - Alternate GPIO SMI Status and Enable Register (ALT_GPIO_SMI)—

Offset 38h, and GPIO_ROUT - GPIO_ROUT Register (GPIO_ROUT)—Offset 58h registers 

for information about routing these Customer GPIOs to SMI or SCI.