Intel C2518 FH8065501516710 Data Sheet

Product codes

FH8065501516710

Intel

Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

527

Volume 2—Real Time Clock (RTC)—C2000 Product Family

Register Map

26.7.1

Registers in I/O Space

The RTC internal registers and RAM are organized as two banks of 128 bytes each,

called the standard and extended banks.

Note:

Disabling the extended bank does not occur.

The first 14 bytes of the standard bank contain the RTC time and date information

along with four registers, A-D, that are used for configuration of the RTC. The extended

bank contains a full 128 bytes of battery backed SRAM. All data movement between the

host CPU and the RTC is done through registers mapped to the standard I/O space.

The Indexed Registers (IR) and Target Registers (TR) are used for data movement to

and from the standard bank. The Extended RAM Index Register (RIR) and Extended

RAM Target Register (RTR) are used for data movement to and from the extended

bank. All of these registers have alias I/O locations as indicated in

T able 26-4

Note:

Writes to 72h, 74h, and 76h do not affect the NMI enable (bit 7 of 70h).

I/O locations 70h and 71h are standard ISA locations for the real time clock. Locations

72h and 73h are for accessing extended RAM. The extended RAM bank is also accessed

using an indexed scheme. The I/O address 72h is used as the address pointer, and I/O

address 73h is used as the data register. Index addresses above 127h are not valid.

26.7.2

Difficulty Accessing These Registers

The registers needed to access the two banks of RTC registers at the I/O locations

0x70-0x77 have been present since the early days of personal computers. They were

originally located in the real time clock circuitry itself before being absorbed into Intel

silicon as PC designs matured. As such, it retains a lot of the legacy limitations inherent

with earlier architectures (aliasing, etc.).

Accessing these registers is difficult. The NMI Enable bit (NMI_EN = I/O 0x70[7]) is

especially troublesome as a straight read of this register returns all 0xFF data, although

writes work fine. Refer to the Intel white paper for guidance:

Accessing the Real Time Clock Registers and the NMI Enable

ftp://download.intel.com/design/intarch/PAPERS/321088.pdf

This paper explains the details and the necessary steps the software needs to perform

to access these registers.

§ §

Table 26-4. RTC Registers in I/O Space

I/O

Address

Alias I/O

Location

If U128E Bit = 0

Default

Value

Name

Description

0x70

74h

Also alias to 72h and 76h

00h

Indexed Registers

0x71

75h

Also alias to 73h and 77h

00h

Target Registers

0x72

76h

00h

RIR

Extended RAM Index Register

(if enabled)

0x73

77h

00h

RTR

Extended RAM Target Register

(if enabled)