Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 3 of 3

September 2014

574

Order Number: 330061-002US

DDR3_0_DQ[63:0]

I/O

DDR

64

VDDQ

DDR3 Data Bus: Memory read 

and write data. Data signal 

interface to the SDRAM data 

bus. These 64-bit signals have 

8-byte lanes, and each byte 

lane has a corresponding 

strobe pair.

DDR3_0_MA[15:0]

O

DDR

16

VDDQ

DDR3 Memory Address: 

Provides multiplexed row and 

column address to memory. 

Provides the row address for 

active commands and the 

column address and Auto-Pre-

charge bit for read/write 

commands to select one 

location out of the memory 

array in the respective bank. 

A10 is sampled during a Pre-

charge command to 

determine whether the Pre-

charge applies to one bank 

(A10 LOW) or all banks (A10 

HIGH). If only one bank is to 

be pre-charged, the bank is 

selected by BA0 - BA2. The 

address inputs also provide 

the op-code during MRS or 

EMRS commands.

DDR3_0_DQS[7:0]

I/O

DDR

8

VDDQ

DDR3 Data Strobes: During 

writes, driven by the CDV 

offset so as to be centered in 

the data phase. During reads, 

driven by memory devices 

edge-aligned with data. The 

following list matches the data 

strobe with the data bytes: 

(DQS_7: DQ[63:56] …. 

DQS_0: DQ[7:0]). The data 

strobes may be used in single-

ended mode or paired with 

optional complementary 

signals DQS_B to provide 

differential-pair signaling to 

the system during both reads 

and writes. A control bit at 

EMR(1)[A10] enables or 

disables all complementary 

data strobe signals.

DDR3_0_DQSECC[0]

I/O

DDR

1

VDDQ

DDR3 ECC Strobe: 

Differential-pair output with 

read-data ECC, differential-

pair input with write-data 

ECC. Edge-aligned with read-

data ECC, centered in write-

data ECC.