Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 3 of 3

September 2014

586

Order Number: 330061-002US

NMI/GPIOS_0

I

CMOS_V3P3

1

20K, PD

V3P3S

NMI: This is an NMI event 

indication to iLB. When 

operating as NMI event 

indication pin function 

(selected via the NMI SMI 

Event Native GPIO Enable soft 

strap), the pin is a push-pull. 

If the NMI interface is not 

used, the signals can be used 

as GPIO Port 0. 

ERROR2_B/GPIOS_1

O

CMOS_V3P3

1

V3P3S

Root port error collector 

output. The platform board 

must ignore this SoC output 

signal while PMU_PLTRST_B 

(active-low SoC output) is 

asserted.If the ERROR2_B 

interface is not used, the 

signals can be used as GPIO 

Port 1. 

ERROR1_B/GPIOS_2

O

CMOS_V3P3

1

V3P3S

Root port error collector 

output. The platform board 

must ignore this SoC output 

signal while PMU_PLTRST_B 

(active-low SoC output) is 

asserted. If the ERROR1_B 

interface is not used, the 

signals can be used as GPIO 

Port 2. 

ERROR0_B/GPIOS_3

O

CMOS_V3P3

1

V3P3S

Root port error collector 

output. The platform board 

must ignore this SoC output 

signal while PMU_PLTRST_B 

(active-low SoC output) is 

asserted. If the ERROR0_B 

interface is not used, the 

signals can be used as GPIO 

Port 3. 

IERR_B/GPIOS_4

O

CMOS_V3P3

1

V3P3S

Internal Error. Catastrophic 

error. Requires immediate 

system shut down. During 

power-up, IERR_B is valid 

after the PMU_PLTRST_B 

(Platform Reset) signal is 

deasserted by the SoC. Before 

the Platform Reset is 

deasserted, the signal may be 

unstable and falsely signal an 

internal error. If the IERR_B 

interface is not used, the 

signals can be used as GPIO 

Port 4.