Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 3 of 3

September 2014

592

Order Number: 330061-002US

FLEX_CLK_SE0/

GPIOS_19

O

CMOS_V3P3

1

V3P3S

Single-ended, flexible, 

general-purpose, 25-MHz 

clock output. Can be 

programmed to be 33 MHz or 

disabled using the CCU 

Dividers Control Register 

(DIV_CTRL) located at 

sideband register Port 40h, 

offset 0Ch. If the 

FLEX_CLK_SE0 interface is 

not used, the signals can be 

used as GPIO Port 19. 

FLEX_CLK_SE1/

GPIOS_20

O

CMOS_V3P3

1

V3P3S

Single-ended, flexible, 

general-purpose, 25-MHz 

clock output. Can be 

programmed to be 33 MHz or 

disabled using the CCU 

Dividers Control Register 

(DIV_CTRL) located at 

sideband register Port 40h, 

offset 0Ch. If the 

FLEX_CLK_SE1 interface is 

not used, the signals can be 

used as GPIO Port 20. 

PCIE_TXP[15:0]

O

LV DIFF

16

V1P0S

PCI Express* Transmit: 

Differential-pair output. 

2.5GT/s and 5.0GT/s data 

rates supported.

PCIE_TXN[15:0]

O

LV DIFF

16

V1P0S

PCI Express Transmit: 

Differential-pair output. 

2.5GT/s and 5.0GT/s data 

rates supported.

PCIE_RXP[15:0]

I LV 

DIFF

16

V1P0S

PCI Express Receive: 

Differential-pair input. 

2.5GT/s and 5.0GT/s data 

rates supported.

PCIE_RXN[15:0]

I LV 

DIFF

16

V1P0S

PCI Express Receive: 

Differential-pair input. 

2.5GT/s and 5.0GT/s data 

rates supported.

PCIE_REFCLKN

I

LV DIFF

1

V1P0S

PCI Express Reference Clock: 

Differential-pair input 100 

MHz. PCIe* PLL Differential 

reference clock for PCIe PLL.

PCIE_REFCLKP

I

LV DIFF

1

V1P0S

PCI Express Reference Clock: 

Differential-pair input 100 

MHz. PCIe PLL Differential 

reference clock for PCIe PLL.

PCIE_OBSP
PCIE_OBSN

O

Analog

2

V1P0S

PCIE RCOMP: Connect the 

PCIE_OBSP pin to the 

PCIE_OBSN pin using a 402-Ω 

±1% resistor.

TOTAL

70