Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 3 of 3
Order Number: 330061-002US
601
Volume 3—Signal Names and Descriptions—C2000 Product Family
RTC Well Signals
31.12
RTC Well Signals
Table 31-15. RTC Well Signals (Sheet 1 of 2)
Signal Name
I/O
Type
I/O Buffer
Type
Ball
Count
Internal
Resistor
PU/PD
External
Resistor
PU/PD
Power
Rail
Description
RTEST_B
I
CMOS_V3P3
1
EXT RC
Circuit
VRTC3P0
SRTCRST_B
.
Note:
This signal may also
be used for debug
purposes, as part of
an XDP port.
RTEST_B
input must
always be high when all other
non-RTC power planes are on.
This signal is in the RTC power
well.
The time delay parameters
The time delay parameters
RSMRST_B
I
CMOS_V3P3
1
EXT PU
VRTC3P0
Resume Well Reset: (active
low). Input asserted by the
External Circuitry (EC) to
reset the registers and
components in the SUS power
well. An external RC circuit is
required to ensure that the
SUS power well voltage is
valid before the deassertion of
the RSMRST_B signal.
COREPWROK
I
CMOS_V3P3
1
VRTC3P0
Core Power OK. Input
asserted by the External
Circuitry (EC) to indicate on
that the power supplied to the
core is stable. PWROK can be
driven asynchronously. The
EC typically uses PWROK to
produce the PERST_B signal
on the PCI Express*
interfaces. The power
associated with the PCI
Express circuitry needs to be
valid for at least 99 ms before
COREPWROK assertion to
comply with the PCI Express
100-ms requirement for
system reset deassertion.