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Intel C2518 FH8065501516710 Data Sheet

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FH8065501516710
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Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 3 of 3
Order Number: 330061-002US
619
Volume 3—Signal Pin States and Termination—C2000 Product Family
Signal Pin States
32.1.1
System Memory Signals
32.1.1.1
DDR3[0] Memory Signals
Table 32-2. System Memory Signals (DDR3[0])
Signal Name
Direction
During Reset 
(PWROK)
Post-Reset
S5
DDR3_0_DQ[63:0]
I/O
High-Z
High-Z
High-Z
DDR3_0_MA[15:0]
O
High-Z
VOL
High-Z
DDR3_0_DQS[7:0]
DDR3_0_DQSECC
I/O
High-Z
High-Z
High-Z
DDR3_0_DQSB[7:0]
DDR3_0_DQSBECC
I/O
High-Z
High-Z
High-Z
DDR3_0_CK[3:0]
O
High-Z
VOH
High-Z
DDR3_0_CKB[3:0]
O
High-Z
VOL
High-Z
DDR3_0_CKE[3:0]
O
High-Z
VOL
VOL
DDR3_0_CSB[3:0]
O
High-Z
VOH
High-Z
DDR3_0_ODT[3:0]
O
High-Z
High-Z
High-Z
DDR3_0_RASB
O
High-Z
VOH
High-Z
DDR3_0_CASB
O
High-Z
VOH
High-Z
DDR3_0_WEB
O
High-Z
VOH
High-Z
DDR3_0_BS[2:0]
O
High-Z
VOL
High-Z
DDR3_0_DRAM_PWROK
I
VIH
VIH
High-Z
DDR3_0_DRAMRSTB
I/O
DDR3_0_VCCA_PWROK
I
VIH
VIH
High-Z
DDR3_0_VREF
I Analog
Analog
High-Z
DDR3_0_ODTPU
I/O
DDR3_0_BS[2:0]
O
High-Z
VOL
High-Z
DDR3_0_DQPU
I/O
DDR3_0_CMDPU
I/O
DDR3_0_MON1P
I/O
DDR3_0_MON1N
I/O
DDR3_0_MON2P
I/O
DDR3_0_MON2N
I/O
DDR3_0_REFP
DDR3_0_REFN
I
Running
Running
High-Z
DDR3_0_DQECC[7:0]
I/O
High-Z
High-Z
High-Z