Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 3 of 3

Order Number: 330061-002US

661

This subsection contains the timing parameters for all four SMBus 2.0 units of the SoC:

• Unit 0 - Legacy, typically for DIMM SPD

— As an SMBus 2.0 Master, provides SMB_CLK0 at 83 kHz.
— Cannot be an SMB 2.0 Target.
— Can be configured to be an I

2

C bus Master, Standard Mode, provides 

SMB_CLK0 at 83 kHz.

• Unit  1  -  Host,  SMT

— As an SMBus 2.0 Master, provides SMB_CLK1 at 80 kHz.
— As an SMB 2.0 Target, can operate at 10 kHz -100kHz.
— Can be configured to be an I

2

C bus Master, Standard Mode, provides 

SMB_CLK1 at 100 kHz.

— Can be configured to be an I

2

C bus Master, Fast Mode, provides SMB_CLK1 at 

400 kHz.

— Can be configured to be an I

2

C bus Master, Fast Mode Plus, provides SMB_CLK1 

at 1000 kHz.

• Unit  2  -  PECI

— As an SMB 2.0 Target, can operate at 10 kHz -100 kHz.
— Cannot be an SMBus 2.0 Master.
— Cannot be configured to be an I

2

C bus Master or Target.

• SMBus GbE - Ethernet Controller

— As an SMBus 2.0 Master, provides GBE_SMBCLK at 84 kHz.
— As an SMB 2.0 Target, can operate at 10 kHz -100 kHz.
— Cannot be configured to be an I

2

C bus Master or Target.

 and 

 show the SMBus 2.0 clock output parameters when the 

SoC controller is the SMBus Master, and when it is an I

2

C Master. The SoC output clock 

conforms with the T

LOW

, T

HIGH

, T

R

, and T

F

 shown in the System Management Bus 

(SMBus) Specification, Version 2.0 and the I

C-bus Specification and User Manual, Rev. 

03 specifications. As a master, the SoC controllers comply with all other timing 

parameters defined by the specifications.

As an SMBus 2.0 or I

2

C Target, each SoC controller conforms to the timing parameters 

defined by the specifications.