Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 3 of 3
Order Number: 330061-002US
669
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
SoC Reference Clock Interfaces
33.16
SoC Reference Clock Interfaces
33.16.1
Host, DDR3, PCI Express, SATA2 Reference Clocks
• HPLL_REF[P, N] - Host Reference Clock, Differential, Spread Spectrum
• DDR3_0_REF[P, N] - DDR3 Memory Controller Channel 0 Reference Clock,
• DDR3_0_REF[P, N] - DDR3 Memory Controller Channel 0 Reference Clock,
Differential, Spread Spectrum
• DDR3_1_REF[P, N] - DDR3 Memory Controller Channel 1 Reference Clock,
Differential, Spread Spectrum
• PCIE_REFCLK[P, N] - PCI Express* Controller Reference Clock, Differential, Spread
Spectrum
• SATA_REFCLK[P, N] - SATA2 Controller Reference Clock, Differential, Spread
Spectrum
shows the required clock period based on:
• PPM Tolerance = 35 ppm
• Cycle-to-Cycle Jitter = 85 ps
• Spread = -0.50%
• Cycle-to-Cycle Jitter = 85 ps
• Spread = -0.50%
has the AC requirements for these reference clock inputs.
Table 33-26. Clock Period Requirements - Differential Input - Spread Spectrum
Center
Frequency
(MHz)
Measurement Window
Clock Period
(ns)
Fig
100.00
1 Clock
- Clock-to-Clock Jitter AbsPer Min
9.88999
1 µs
-SSC Short-Term Average Min
9.97499
0.1 sec
- ppm Long-Term Average Min
9.99999
0.1 sec
0 ppm Period Nominal
10.00000
0.1 sec
+ ppm Long-Term Average Max
10.00035
1 µs
+SSC Short-Term Average Max
10.02535
1 Clock
+ Clock-to-Clock Jitter AbsPer Max
10.11035