Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
SoC Reset and Power Management Unit (PMU) Interface
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
678
Order Number: 330061-002US
33.19
SoC Reset and Power Management Unit (PMU) Interface
33.19.1
DC Specifications
 contain the DC specifications for the Reset and Power 
Management interface signals.
This signal is in the 3.3V Core power well of the SoC. Se
.
• PMU_RESETBUTTON_B (Input)
These signals are in the 3.3V SUS power well of the SoC. See 
• PMU_WAKE_B (Input)
• PMU_PWRBTN_B (Input)
• PMU_PLTRST_B  (Output)
• PMU_SLP_LAN_B (Output)
• PMU_SLP_S3_B (Output)
• PMU_SLP_S45_B (Output)
• PMU_SLP_DDRVTT_B  (Output)
• SUSPWRDNACK  (Output)
• SUS_STAT_B  (Output)
• CPU_RESET_B (Output)
33.19.2
Interface Timing Parameters and Waveforms
The PMU interface signals, their state exchange and timing with the platform board 
design are in 
Table 33-38. PMU_RESETBUTTON_B Signal DC Specifications
Symbol
Parameter
Min
Max
Unit
Note
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2.0
V3P3S+0.3
V
Table 33-39. Reset and Power Management Signal DC Specifications
Symbol
Parameter
Min
Max
Unit
Note
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2.0
V3P3A+0.3
V
V
OL
Output Low Voltage
0.4
V
@ 4 mA
V
OH
Output High Voltage
2.4
V3P3A
V
@ –4 mA