Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

75

The Machine Check Architecture (MCA) and Machine Check Exception (MCE) are 

model-specific features. Software can execute the CPUID instruction (with EAX = 1) to 

determine that the particular core processor implements these features. Following the 

execution of the CPUID instruction (with EAX = 1), the SoC settings of the MCA feature 

bit 14, and MCE feature bit 7, are both set to 1 indicating that the features are 

available.

1. Execute the CPUID instruction with EAX = 0. Check that the returned vendor ID 

equals Genuine Intel.

2. Execute the CPUID instruction with EAX = 1 to get the feature flags. Ensure that 

the MCA feature flag (bit 14) is set to a 1 and the MCE feature flags (bit 7) is set to 

a 1.

3. Read the Machine Check Capabilities register (IA32_MCG_CAP, MSR 179h) and get 

the bank count from IA32_MCG_CAP[7:0]. The value is 6 indicating that banks 0 

through 5 exist for the SoC. Bank 0 MSRs begin at MSR 400h.

4. Read IA32_MCG_CAP[9]. This value is 0 in that extended state registers are not 

supported by the SoC.

5. Read IA32_MCG_CAP[8]. This value is 0 in that the IA32_MCG_CTL register (MSR 

17Bh) is not supported by the SoC.

6. The BIOS writes all 1s to the six IA32_MCi_CTL registers. The “i” indicates banks 0 

through 5.

7. Only if power-on RESET# occurred, the IA32_MCi_STATUS registers are cleared.
8. If power-on RESET# was not detected, then the BIOS may optionally log the 

reported errors as a CPU error or an other equivalent platform error in an event 

log.

IA32_P5_MC_ADDR (MSR 0h)

IA32_P5_MC_TYPE (MSR 1h)

Newer software should not use the two P5 Compatibility MSRs. In the context of P5 the 

SoC does not return anything meaningful. Instead, the software needs to use 

IA32_MC0_STATUS (MSR 401h) instead of MSR 1h and IA32_MC0_ADDR (MSR 402h) 

instead of MSR 0h.