Intel C2350 FH8065401488914 Data Sheet
Product codes
FH8065401488914
Volume 2—Interrupt Architecture—C2000 Product Family
PCI Interrupts and Routing
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
116
Order Number: 330061-002US
There are 32, 16-bit PCI interrupt routing registers, one for each of the 32 possible PCI
device addresses. These 32 registers, named IR0 through IR31, are located in memory
space and begin at the memory address specified by ILB_BASE_ADDRESS, offset 20h.
Each 16-bit register has four 4-bit fields:
• IRA: INTA# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IRB: INTB# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IEC: INTC# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IRD: INTD# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IRB: INTB# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IEC: INTC# mapping to one of PIRQA# through PIRQH# (0h through 7h)
• IRD: INTD# mapping to one of PIRQA# through PIRQH# (0h through 7h)
The field values 8h through Fh are reserved and must not be used.
Note:
Each of the eight PIRQx# can represent the interrupt of more than one device and up
to four for each device.
PIRQA# through PIRQH# are then each inverted and routed to the I/O APIC and to the
8259 PIC.
PIRQA through PIRQH are connected to the I/O APIC inputs IRQ16 through IRQ23,
respectively. Information about programming the I/O APIC is in
For connecting to the 8259 PIC, there are eight, 8-bit routing control registers, one for
each PIRQA through PIRQH. Each of the eight interrupts are routed to one of 11 IRQ
inputs of the integrated 8259 PIC according to its programmed IRQ Routing (IR) field.
The PIRQx is routed to the 8259 PIC provided that its Interrupt Routing Enable (REN)
bit is programmed to 0. When REN is programmed as 1, the particular PIRQx is not
routed to the 8259 PIC. These eight registers, named PIRQA through PIRQH, are
located in the memory space and begin at the memory address specified by the
ILB_BASE_ADDRESS, offset 8h.
PIRQA# through PIRQH# are defined as Level-Sensitive interrupts. When routed to a
specified IRQ line, the software must change the corresponding ELCR1 or ELCR2
register of the 8259 to a Level-Sensitive mode. Information about programming the