Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

121

1.

GCFG.LRE is the Legacy Rout Enable (LRE) bit 1 of the HPET General Configuration (GCFG) Register 

located at the memory-space address FED0_0010h.

2.

When GCFG.LRE is set, the HPET T0C.IR and T1C.IR bits have no impact for timers 0 and 1. T0C and 

T1C are located at the memory-space addresses FED0_0100h and FED0_0120h, respectively.

3.

When GCFG.LRE is cleared, each of the three HPET timers has its own routing control. The interrupts 

can be routed to various interrupts in the I/O APIC. T0C.IRC, T1C.IRC, and T2C.IRC indicate which 

interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not 

be shared with any other interrupts.

4.

HPET Timer 2 is routed to the APIC as per the routing in the HPET T2C register located at the memory-

space addresses FED0_0140h.

5.

For routing of SCI, see 

The I/O APIC has a Redirection Table (RT) with an entry for each interrupt source. Each 

RT entry is individually programmed for trigger mode (edge or level), vector number, 

and destination processor(s). The interrupt is reported to the appropriate local APIC(s).

For more information about the I/O APIC, see