Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

134

Order Number: 330061-002US

6. The SoC now enters the S5 (Soft Off) state as asserts the active-low 

PMU_SLP_S45_B output signal to the platform board.

7. The platform board responds by deasserting the active-high, 

DDR3_0_DRAM_PWROK, and DDR3_1_DRAM_PWROK input signals of the SoC.

8. The platform board removes the VDDQ (VDDQA and VDDQB) voltages from the 

SoC.

9. The SoC is now ready to exit the S5 (Soft Off) state.

Refer to 

 for steps 10 through 20:

10. The SoC now exits the S5 (Soft Off) state by deasserting the active-low 

PMU_SLP_S45_B output signal to the platform board

11. VDDQ (VDDQA/VDDQB)

— When VDDQ is valid, the platform asserts the DDR3_0_DRAM_PWROK and 

DDR3_1_DRAM_PWROK. The SoC receivers for these signals are powered by 

VDDQ.

— The SoC is now in the S3 state. Because the SoC does not support S3, the SoC 

does not remain in S3.

— When the SoC is ready to exit the S3 state and advance to the S0 state, it 

deasserts the output signals PMU_SLP_S3_B and PMU_SLP_DDRVTT_B. The 

platform board design may use the PMU_SLP_DDRVTT_B signal to provide 

power to the SDRAM components.

12. This step is optional: Wait for PMU_SLP_S3_B and PMU_SLP_DDRVTT_B output 

signals to de-assert.

13. VNN and VCC may begin to ramp-up together.
14. Once VNN and VCC voltages are valid and stable at the SoC pins, VCCSRAM may 

begin to ramp-up at the SoC pins no later than 5 ms. Designers should make this 

delay as short as possible.

15. As VCC begins to ramp-up, V1P35S may begin to ramp-up.
16. Once VNN voltage is valid and stable, V1P0S may begin to ramp-up.
17. Once V1P0S begins to ramp-up, V1P8S may begin to ramp-up.
18. VNN, VCC, VCCSRAM, V1P35S, V1P0S, and V1P8S are valid and stable.
19. V3P3S may begin to ramp-up.
20. Once the platform board has all of the DDR3 and core power well voltage supplies 

at their valid voltages, and all of the reference clocks are stable at the SoC input 

pins, it asserts the COREPWROK signal to the SoC. At the same time, the platform 

also asserts the DDR3_0_VCCA_PWROK and DDR3_1_VCCA_PWROK SoC input 

signals.

21. The SoC then deasserts SUS_STAT_B and platform reset (PMU_PLTRST_B).

The platform board and the SoC are now ready to function in the S0 state. The SoC 

internal reset for the core CPU used for the BIOS is completed, and the BIOS 

instruction fetching begins from the Flash memory. This core reset is also used for the 

SoC output signal, CPU_RESET_B, which the platform board provides to the In-Target 

Probe (ITP) connector if part of the board design. It is used only for debug purposes.