Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

328

Order Number: 330061-002US

Once the firmware has completed initialization, the hardware target logic continues to 

idle until an external SMBus master sends a transaction.

External Master Initiating Writes

1. Once the hardware receives a write transaction targeting one of its slave 

addresses, the hardware responds to the address and command phases.

2. Each byte ACKed is eventually DMAed to the memory starting at location 

Base + HWtHeadPtr + 4B as Dword writes.

3. Once the transaction is completed, the hardware writes the final bytes to memory 

(PBC field in the header indicates to the firmware how many true bytes are in the 

payload).

4. Upon completion of the transaction, the hardware writes the header Dword of that 

transaction into the location pointed to by HWtHeadPtr. This contains all the status 

information for the transaction. (See 

5. The hardware then updates the HWtHeadPtr to the next free Dword location in the 

target memory.

6. The hardware then writes interrupt information to the Dwords as pointed to by 

SMTICL. (See 

a. The hardware writes the current value of the HWtHeadPtr to TRGT.HTHP and sets 

TRGT.VALID.

b. Also, if the transaction terminated abnormally the error condition is written 

(e.g., to ERR.TRBAF, ERR.TRBF, ERR.CKLTO) and ERR.VALID is set to indicate an 

error was present.

c. Finally, if enabled, the hardware then sends MSI to the firmware.