Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

337

TTYPE = 0001, 0010 and MTYPE = 0000

SMT supports being a target of certain SMBus and I

2

C transactions (see 

), and it acknowledges transactions directed to 

either of its two target addresses (TACTRL.ADDR0 or TACTRL.ADDR1). The basic flow is 

depicted in 

. In general the target hardware interface is agnostic of 

command and PEC bytes. The firmware handles these bytes.

It is assumed that block reads to SMT as a target are directed only to the dedicated 

GPBR address (GPBRCTRL.GPTRADR) and are not considered in this flow.

Write cycles received by the SMT target interface nominally terminate when the 

external master produces a Stop condition. Premature hardware NACK occurs if the 

interface is busy or overflows. The SMBus Quick Command is comprised only of the 

address byte, with the data encoded entirely within the R/W# bit; all other SMBus and 

I

2

C transactions have additional data bytes.

The optional PEC byte is not shown explicitly because the firmware determines the 

actual presence of PEC. This provides for PEC to be enabled on a per-function, per-

address, per-protocol, or even per-transaction basis. The hardware always performs a 

speculative internal PEC calculation, which it then compares to the final received byte. 

If the received and calculated bytes match, this is a strong indication that the 

transaction was PEC-enabled, but the firmware has the final authority. Conversely, a 

mismatch is not proof of a transmission error—it may have been a PEC-less 

transaction. In this case, the firmware ignores the PEC status flag in the target 

descriptor TSTS field, which resulted from the hardware invalid speculative PEC 

comparison.

Since some protocols have identical transmission templates it is also the responsibility 

of the firmware to prevent or resolve apparent aliasing. (e.g., aliasing of Send Byte 

with PEC and Write Byte; aliasing of Write Byte with PEC and Write Word; aliasing of 

SMBus Write Byte and I

2

C MTx-to-SRx.) It is assumed this is accomplished through 

negotiation between the firmware and the external master. For instance, the command 

byte differentiates protocols or certain protocol combinations are excluded.

A special case of aliasing occurs for SMBus Block Write. Since the hardware ignores the 

command byte, it cannot distinguish Block Write Byte Count from an ordinary data 

byte. Therefore, the hardware captures and pushes all bytes to the firmware for 

processing, and the hardware is not required to verify the received byte count. In 

target mode, the firmware programs a ceiling (TRxCTRL.MRxB) on the write length 

such that if a transaction overflows the ceiling then the hardware must NACK any 

unexpected data bytes. This ceiling must not exceed the buffer size. The hardware 

NACK flag in the target descriptor TSTS field is set upon a hardware (buffer) overflow, 

but this flag does not comprehend overflow of an individual protocol (e.g., a Block Write 

where received bytes > indicated Byte Count).

If a target address receives both I

2

C and SMBus protocols the maximum permitted 

write length (TRxCTRL.MRxB) must accommodate both. For example, if a target 

receives SMBus Block Write with PEC the write length must be greater than or equal to 

36 bytes (= address + command + byte count + N data bytes + PEC, where N <= 32).

If the firmware has declared a matched address to be busy (TPOLICY.ADDR0BSY or 

TPOLICY.ADDR1BSY) then the hardware will ACK the address byte but NACK all 

subsequent bytes.

The hardware address matching after any SMBus repeated-start condition is subject to 

SUSCHKB.IRWRST; if asserted it causes the hardware to ignore the R/W# bit during 

matching. This behavior is not shown in the flowchart.