Intel C2350 FH8065401488914 Data Sheet
Product codes
FH8065401488914
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Register Maps
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
354
Order Number: 330061-002US
§ §
Target Registers - ARP
280h
SMT Address Resolution Protocol Control Register (SMTARPCTRL)
284h - 28Ch
Reserved
290h
UDID0 Data Register (UDID0)
298h
UDID0 Upper Data Register (UUDID0)
2A0h
UDID1 Data Register (UDID1)
2A8h
UDID1 Upper Data Register (UUDID1)
2ACh - 2BCh
Reserved
Target Registers - Reserved
2C0h - 2FCh
Reserved
PHY Registers
300h
SMBus PHY Global Timing Register (SPGT)
304h
SMBus PHY Master Timing Register (SPMT)
308h
SMBus PHY Slave Timing Register (SPST)
30Ch
SMBus Fair Timing Register (SMBFT)
310h
Clock Low Time-out Control Register (CLTC)
314h - 37Ch
Reserved
Debug Registers
380h
Dynamic Clock Gating Register (DCLKGT)
384h
SUS Well Chicken Bits Register (SUSCHKB)
388h
Debug Control Register (DBCTRL)
38Ch
Debug Status Register (DBSTS)
390h and remaining
Reserved
Table 15-33. Memory Space Address and Description (Sheet 2 of 2)
Address Offset
Register Description and Name