Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

370

Order Number: 330061-002US

8

+ 20

11:0

PCIe Slot Width

PCIe Slot Width is used to set the slot width for each PCIe Root 

Port.
Bits [11:09] are used for PCIe RP4.
Bits [08:06] are used for PCIe RP3.
Bits [05:03] are used for PCIe RP2.
Bits [02:00] are used for PCIe RP1.

The encoding for each set of 3 bits is:
3’b000 = Physical port width
3’b001 = x1
3’b010 = x2
3’b011 = x4
3’b100 = x8 only valid for RP1 and RP3
3’b101 = x16 only valid for RP1

The Bifurcation Control register (BIFCTL0) impacts 

these soft straps.

12’h0

8

+ 20h

15:12

Reserved

Reserved

1’b0

8

+ 20h

16

PCIe RP1

Disable

PCIe Root Port 1 (B0:D1) Disabled: 
1'b0 (false) - Enabled
1'b1 (true) - Disabled

Ensure these soft straps are set to match this selection.

• SoC Strap 0 PCIe RP1 (B0:D1) Disable

• SoC Strap 5 PCIe Lane Power Enable 0
• SoC Strap 5 PCIe Lane Power Enable 1
• SoC Strap 5 PCIe Lane Power Enable 2
• SoC Strap 5 PCIe Lane Power Enable 3

1'b0

8

+ 20h

17

PCIe RP2

Disable

PCIe Root Port 2 (B0:D2) Disabled: 
1'b0 (false) - Enabled
1'b1 (true) - Disabled

Ensure these soft straps are set to match this selection.

• SoC Strap 0 PCIe RP2 (B0:D2) Disable

• SoC Strap 5 PCIe Lane Power Enable 0
• SoC Strap 5 PCIe Lane Power Enable 1
• SoC Strap 5 PCIe Lane Power Enable 2
• SoC Strap 5 PCIe Lane Power Enable 3
• SoC Strap 5 PCIe Lane Power Enable 4
• SoC Strap 5 PCIe Lane Power Enable 5
• SoC Strap 5 PCIe Lane Power Enable 6
• SoC Strap 5 PCIe Lane Power Enable 7

1'b0