Intel C2350 FH8065401488914 Data Sheet

Intel

Product codes

FH8065401488914

Contents—C2000 Product Family

Intel

®

Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet

Order Number: 330061-002US

5

Fatal Errors.......................................................................................... 69

Non-Fatal Errors ................................................................................... 69

Software Correctable Errors ................................................... 69

Global Error Reporting ....................................................................................... 70
4.7.1

Reporting Errors to CPU ......................................................................... 72

Non-Maskable Interrupt (NMI) ............................................... 72

System Management Interrupt (SMI) ...................................... 72

Reporting Global Errors to an External Device ........................................... 72

Machine Check Architecture.................................................................... 72

Machine Check Availability and Discovery ................................ 75

P5 Compatibility MSRs .......................................................... 75

Machine Check Global Control MSRs........................................ 76

Machine Check Error-Reporting MSR Banks 0-5 ........................ 77

Error-Status Cloaking Feature................................................................. 88

Hide Corrected-Error Status From OS...................................... 88

SMI for MCA Uncorrected Errors ............................................. 88

MCERR/IERR Signaling .......................................................................... 89

PCI Express INTx and MSI...................................................................... 89

Error Register Overview......................................................................... 90

Local Error Registers............................................................. 91

Global Error Registers ........................................................... 93

System Error (SERR) ............................................................ 95

First and Next Error Log Registers .......................................... 95

Error Register Flow ............................................................... 96

Error Counters ..................................................................... 97

SoC Error Handling Summary ............................................................................. 98

Register Map .................................................................................................. 105

4.10 System Agent Register Map .............................................................................. 106

Registers in Configuration Space........................................................... 106

4.11 RAS Register Map............................................................................................ 107

Registers in Configuration Space........................................................... 107

4.12 Root Complex Event Collector (RCEC) Register Map ............................................. 109

Registers in Configuration Space........................................................... 109

Clock Architecture.................................................................................................. 111
5.1

Input Clocks ................................................................................................... 113

Output Clocks ................................................................................................. 114

Interrupt Architecture ........................................................................................... 115
6.1

PCI Interrupts and Routing ............................................................................... 115

Non-Maskable Interrupt (NMI) .......................................................................... 118

System Management Interrupt (SMI) ................................................................. 118

System Control Interrupt (SCI) ......................................................................... 119

Message Signaled Interrupt (MSI and MSI-X) ...................................................... 119

I/O APIC Input Mapping ................................................................................... 120

8259 PIC Input Mapping................................................................................... 122

Device Interrupt-Generating Capabilities ............................................................ 123

SoC Reset and Power Supply Sequences ................................................................ 125
7.1

Power Up from G3 State (Mechanical Off) ........................................................... 125
7.1.1

While in the G3 State .......................................................................... 125

Powering-Up for the First Time ............................................................. 125

SUS Power Well Power-Up Sequence From the G3 State........................... 126

Core Power-Up Sequence..................................................................... 129

Reset Sequences and Power-Down Sequences..................................................... 133
7.2.1

Cold Reset Sequence........................................................................... 133

SUSPWRDNACK ................................................................. 138