Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

549

1.

Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, and IRQ8#.

2.

The slave 8259 controller is cascaded onto the master 8259 controller through the master controller 

interrupt input IRQ2.

3.

For routing of the PIRQA through PIRQH interrupts, see 

The SoC cascades the slave controller onto the master controller through the master 

controller interrupt input 2. This means only 15 interrupts exist for the SoC PIC.

Active-low interrupt sources (such as PIRQ#) are inverted inside the SoC. In the 

following descriptions of the 8259s, interrupt levels are in reference to signals at the 

internal interface of the 8259s after the required inversions have occurred. Therefore, 

the term high indicates active, which means low on an originating PIRQ#.

IRQ13

Slave IRQ5

• GPIO

IRQ14

Slave IRQ6

• SERIRQ (14), or
• IRQ15 from ISA IDE Interrupt, or
• PIRQx

3

IRQ15

Slave IRQ7

• SERIRQ (15), or
• PIRQx

3