Intel C2350 FH8065401488914 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 3 of 3

Order Number: 330061-002US

605

PMU_WAKE_B/

GPIO_SUS8

I

CMOS_V3P3

1

20K, PU

V3P3A

PCI Express* Wake-up Event: 

(active low). Open-Drain input 

signal that is asserted by a 

PCI Express port indicating it 

wants to wake-up the system. 

This is a single signal, named 

WAKE# by the PCI Express 

specification that can be 

driven by any of the PCI 

Express devices implemented 

on the platform board. The 

device indicating the wake-up 

drives this signal low. If the 

PMU_WAKE_B interface is not 

used, the signal can be used 

as GPIO SUS Port 8. 

PMU_PWRBTN_B/

GPIO_SUS9

I

CMOS_V3P3

1

20K, PU

V3P3A

Causes SMI# or SCI to 

indicate to the system request 

to go to a sleep state. If the 

system is in the S5 (Soft-Off) 

state, it causes a wake event. 

If PWRBTNB is pressed for 

more than 4 seconds, it 

causes an unconditional 

transition (power button 

override) to the S5 state. If 

the PMU_PWRBTN_B interface 

is not used, the signal can be 

used as GPIO SUS Port 9. 

PMU_RESETBUTTON_B/

GPIOS_30

I

CMOS_V3P3

1

20K, PU

V3P3S

This pin forces a reset after 

being debounced. If the 

PMU_RESETBUTTON_B 

interface is not used, the 

signals can be used as GPIO 

Port 30. 

PMU_PLTRST_B

O

CMOS_V3P3

1

V3P3A

Platform Reset; The SoC 

asserts PLTRST_B as the main 

SoC platform reset.

SUS_STAT_B/

GPIO_SUS10

O

CMOS_V3P3

1

V3P3A

This signal is asserted by the 

SoC to indicate that the 

system is entering a low-

power state soon. This can be 

monitored by devices with 

memory that need to switch 

from normal refresh to 

suspend refresh mode. It can 

also be used by other 

peripherals as an indication 

that the devices should isolate 

the outputs that may be going 

to powered-off planes. If the 

SUS_STAT_B interface is not 

used, the signal can be used 

as GPIO SUS Port 10. 

TOTAL

12