Intel C2350 FH8065401488914 Data Sheet
Product codes
FH8065401488914
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
DDR3 Memory Interface
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
632
Order Number: 330061-002US
V
OH
Output High Voltage
-
VDDQ -
((VDDQ /
2)* (R
O
N/
(R
ON
+R
VTT_
TERM
))
-
V
2, 5,
7
Reference Clock Signals
R
ON
DDR3L Clock Buffer On Resistance
26
-
40
Ω
6
Command Signals
R
ON
DDR3 Command Buffer On Resistance
18
-
32
Ω
6
R
ON
DDR3 Reset Buffer On Resistance
-
-
40
Ω
6
V
OL
Output Low Voltage, signals:
DDR3_0_DRAMRSTB
DDR3_1_DRAMRSTB
-
-
0.2*VDDQ
V
1, 2
V
OH
Output High Voltage, signals:
DDR3_0_DRAMRSTB
DDR3_1_DRAMRSTB
0.9*VDDQ
-
-
V
1, 2
Control Signals
R
ON
DDR3 Control Buffer On Resistance
18
-
32
Ω
6
DDR3 Miscellaneous Signals
V
IL
Input Low Voltage, signals:
DDR3_0_DRAM_PWROK,
DDR3_1_DRAM_PWROK
-
-
0.55*VDDQ
- 0.2
V
2, 3,
10
V
IH
Input High Voltage, signals:
DDR3_0_DRAM_PWROK,
DDR3_1_DRAM_PWROK
0.55*VDDQ
+ 0.2
-
-
V
2, 4,
5, 10
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all supported SDRAM frequencies.
2.
Voltage rail VDDQ is 1.50V or 1.35V nominal depending on the voltage of all DIMMs connected to the SoC.
3.
V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4.
V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
5.
V
IH
and V
OH
may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality
specifications.
6.
This is the pull-down driver resistance. Refer to processor signal integrity models for I/V characteristics. Reset drive
does not have a termination.
7.
R
VTT_TERM
is the termination on the DIMM and not controlled by the SoC. Refer to the applicable UDIMM/SODIMM
datasheet.
8.
COMP resistance must be provided on the system board with 1% resistors. DDR_RCOMP resistors are terminated to
VSS.
9.
Input leakage current is specified for all DDR3 signals.
10.
DDR3_0_DRAM_PWROK and DDR3_1_DRAM_PWROK must have a maximum of 15-ns rise or fall time over
VDDQ * 0.55± 200 mV and the edge must be monotonic.
Table 33-1. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Note