Intel C2350 FH8065401488914 Data Sheet
Product codes
FH8065401488914
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
86
Order Number: 330061-002US
4.7.3.4.15
Bank 4 — FEC IA32_MC4_ADDR (MSR 412h)
The IA32_MC4_ADDR registers contain the full-physical address of the cache access
that caused the last update to the IA32_MC4_STATUS register.
4.7.3.4.16
Bank 5 — SSA IA32_MC5_CTL (MSR 414h)
This document does not provide details of the individual Error-Reporting Enable flags of
the 64-bit IA32_MC5_CTL register. Refer to the general description of “IA32_MCi_CTL.”
4.7.3.4.17
Bank 5 — SSA IA32_MC5_STATUS (MSR 415h)
This is a 64-bit register with read/write, zero-to-clear, sticky access. The
IA32_MC5_STATUS register follows the descriptions shown for IA32_MCi_STATUS in
Volume 3, Chapter 15 of the Intel
®
64 and IA-32 Architectures Software Developer’s
Manual:
• Bit 63 = VAL - IA32_MC5_STATUS register valid.
• Bit 62 = OVER - Error overflow. Indicates a second error occurred while a previous
• Bit 62 = OVER - Error overflow. Indicates a second error occurred while a previous
error was still valid.
• Bit 61 = UC - Uncorrected error. Is 0 for corrected error.
• Bit 60 = EN - Error reporting enabled.
• Bit 59 = MISCV - IA32_MC5_MISC register valid. This is always 0.
• Bit 58 = ADDRV - IA32_MC5_ADDR register valid.
• Bit 57 = PCC - Processor context corrupted, uncorrected error.
• Bits [56:53] = Reserved.
• Bits [52:38] = Other Information (IA32_MCG_CAP bit 10 is 0) - See the additional
• Bit 60 = EN - Error reporting enabled.
• Bit 59 = MISCV - IA32_MC5_MISC register valid. This is always 0.
• Bit 58 = ADDRV - IA32_MC5_ADDR register valid.
• Bit 57 = PCC - Processor context corrupted, uncorrected error.
• Bits [56:53] = Reserved.
• Bits [52:38] = Other Information (IA32_MCG_CAP bit 10 is 0) - See the additional
Other Information bit definition below.
— Bit 52 = Corrected Overflow - When set, indicates an overflow of the corrected
error count.
— Bits [51:38] = Corrected Error Count - Value indicates the number of corrected
errors received.
• Bits [37:32] = Other Information - Bank specific.
— Bit 37 = Internal Buffer RAM Error.
1 - Indicates a parity error was detected on the internal buffer RAM.
0 - Indicates a data error was received from a PFI- or IDI-requesting agent.
0 - Indicates a data error was received from a PFI- or IDI-requesting agent.
— Bits [36:32] = Value represents the identification of a requesting agent that
forwarded a data error to the SSA.Bits [31:16] = MSCOD Model-Specific Error
Code - Bank specific. For the SoC, this bit field is described in
.
• Bits [15:0] are the bank-specific MCA error code for the MEC.
shows
these error codes and the treatment of the PCC (bit 57), ADDRV (bit 58), and UC
(bit 61) fields of IA32_MC5_STATUS.