Intel C2350 FH8065401488914 Data Sheet

Product codes

FH8065401488914

Intel

Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

Volume 2—System Agent and Root Complex—C2000 Product Family

Global Error Reporting

4.7.5

MCERR/IERR Signaling

The SoC escalates machine check errors (MCERR_B) and unrecoverable internal errors

(IERR_B) to the external BMC and to the CPU cores for handling non-maskable and

other fatal errors in the system. See

Figure 4 -6

. The MCERR and IERR signals are

broadcast to the CPU and to the external platform.

The IERR signal signifies a catastrophic internal error, a condition which requires

immediate attention or possibly shutdown. When this error occurs, the processor core

may not be able to execute reliably through the INT18 handler. The following are some

possible cases of such catastrophic errors:

• Retirement watchdog time-out from the core.
• Internal error detected by the SoC power management circuitry.

The MCERR signal signifies a machine check error occurred and that SoC Machine

Check Architecture registers, accessible through the MSRRD and MSRWR instructions,

may have additional information concerning the error.

Note:

Board designs must not consider IERR_B and MCERR_B valid until after the

PMU_PLTRST_B (Platform Reset) signal is deasserted by the SoC. When the SoC is

powered-up or a cold boot, the IER R_B and MCERR_B signals may be unstable and

falsely signal an internal error or machine check error before the platform reset is

deasserted by the SoC.

4.7.6

PCI Express INTx and MSI

PCIe* INTx and MSI are supported through the PCIe standard error reporting. The SoC

forwards the MSI generated from the downstream PCIe devices to the CPU. Also, PCIe

Root Ports and the Root Complex Event Collector (RCEC) in the SoC generates

INTx/MSI interrupts for error reporting if enabled. Refer to the PCI Express Base

Specification, Revision 2.1 for more details on the PCIe standard and the Advanced

Error Reporting (AER) capability.

Figure 4-6. MCERR and IERR Handling

SoC

L2 Cache

Bus Interface

Core 0

MC
E

MC
ER
R

Core 1

L2 Cache

Bus Interface

Core 0

MCER

IER
R

MC
E

Core 1

L2 Cache

Bus Interface

Core 0

MCER

IER
R

MC
E

Core 1

L2 Cache

Bus Interface

Core 0

MCER

IER
R

MC
E

Core 1

from Power

Management

To external

Management

Controller

MCERR_B

IERR_B

from Uncore

IERR

MCERR