Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1805
16.6.37
SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h
Access Method
Default: 00h
16.6.38
Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh
Access Method
Default: 0000h
5:4
0h
RO
Number of Interrupt Pins (num_int_pin):
This field indicates support of interrupt
input pins for shared bus system. Three asynchronous interrupt pins are defined,
INT_A#, INT_B# and INT_C#. Which interrupt pin is used is determined by the system.
Each one is driven by open drain and then wired OR connection is possible.
•
•
00b = Interrupt Input Pin is not supported
•
01b = INTA is Supported
•
10b = INTA and INTB are supported
•
11b = INTA, INTB and INTC are supported
3
0b
RO
RSVD5:
Reserved
2:0
0h
RO
Number of Clock Pins (num_clk_pin):
This field indicates support of clock pins to
select one of devices for shared bus system. Up to 7 clock pins can be supported.
Shared bus is supported by specific system. Then the Standard Host Driver does not
support control of these clock pins.
•
•
000b Shared bus is not supported
•
001b 1 SDCLK pin is supported
•
010b 2 SDCLK pins are supported
•
. . .
•
111b 7 SDCLK pins are supported
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
spi_int_support
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
00h
RW
SPI Interrupt Support (spi_int_support):
This bit is set to indicate the assertion of
interrupts in the SPI mode at any time, irrespective of the status of thecard select (CS)
line. If this bit is zero, then SDIO card can only assert the interrupt line in the SPI mode
when the CS line is asserted.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h