Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2812
Datasheet
Figure 111.Programmable Serial Protocol Format
NOTE: When in PSP format, if the SSP is the master of the clock (I2Sx_CLK is an output) and the SSPSP.ETDS bit
is cleared, the End of Transfer Data State for the I2Sx_DATAOUT line is 0. If the SSP is the master of the
clock, and the SSPSP.ETDS bit is set, the I2Sx_DATAOUT line remains at the last bit transmitted (LSB). If
the SSP is a slave to the clock (I2Sx_CLK is an input), and modes 1 or 3 are used, the ETDS can only
change from the LSB if more clocks (I2Sx_CLK) are sent to the SSP (i.e., dummy stop clocks or slave
clock is free running.
clock, and the SSPSP.ETDS bit is set, the I2Sx_DATAOUT line remains at the last bit transmitted (LSB). If
the SSP is a slave to the clock (I2Sx_CLK is an input), and modes 1 or 3 are used, the ETDS can only
change from the LSB if more clocks (I2Sx_CLK) are sent to the SSP (i.e., dummy stop clocks or slave
clock is free running.
Figure 112.Programmable Serial Protocol Format (Consecutive Transfers)
LSB
End of Transfer
Data State
MSB
LSB
MSB
T1
T2
T5
T6
T3
T4
SSPSP.SCMODE
I2Sx_CLK
00
01
10
11
I2Sx_DATAOUT
I2Sx_DATAOUT
SSPSP.SFRMP=1
SSPSP.SFRMP=0
I2Sx_FRM
SSPSP.SCMODE
I2Sx_DATAOUT
I2Sx_FRM
I2Sx_CLK
00
01
10
11
I2Sx_DATAOUT
SSPSP.SFRMP=1
SSPSP.SFRMP=0
MSB
LSB
MSB
LSB
MSB
MSB
LSB
LSB
T1
T1
T2
T3
T4
T4
T3
T2
T5
T6
T5
T6
End of Transfer
Data State
End of Transfer
Data State