Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3881
26.8.4
Cache Line Latency Header and BIST (CLLATHEADERBIST)—
Offset Ch
Access Method
Default: 00800000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
MULFNDE
V
HE
ADE
R
TY
PE
LA
TT
IM
E
R
CA
CH
ELINE
_
S
IZE
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO
Reserved0:
Reserved.
23
1h
RO
Multi Function Device (MULFNDEV):
This bit is always 0 for non fabric ports. For
Fabric ports it is driven from fabric_mult_function strap.
•
•
1 = multifunction device
•
0 = single function device
22:16
00h
RO
Header Type (HEADERTYPE):
Implements Type 0 Configuration header.
15:8
00h
RO
Latency Timer (LATTIMER):
Does not apply to PCI Express. Hardwired to 00h.
7:0
00h
RW
Cache Line Size (CACHELINE_SIZE):
Doesn't apply to PCI Express. PCI Express spec
requires this to be implemented as a R/W register but has no functional impact on the
AHB Device connected.