Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
4126
Datasheet
26.18.5
Base Address Register (BAR)—Offset 10h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
MULFNDEV
HE
AD
E
R
T
Y
PE
LA
TT
IMER
CA
CH
ELI
N
E
_
SI
ZE
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO
Reserved0:
Reserved.
23
1h
RO
Multi Function Device (MULFNDEV):
This bit is always 0 for non fabric ports. For
Fabric ports it is driven from fabric_mult_function strap.
•
•
1 = multifunction device
•
0 = single function device
22:16
00h
RO
Header Type (HEADERTYPE):
Implements Type 0 Configuration header.
15:8
00h
RO
Latency Timer (LATTIMER):
Does not apply to PCI Express. Hardwired to 00h.
7:0
00h
RW
Cache Line Size (CACHELINE_SIZE):
Doesn't apply to PCI Express. PCI Express spec
requires this to be implemented as a R/W register but has no functional impact on the
AHB Device connected.
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B
ASE
A
D
DR
S
IZE
IND
ICA
TO
R
PREFE
TC
H
A
B
LE
TY
PE
ME
S
S
A
G
E_
SP
AC
E
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
00000h
RW
Base Address (BASEADDR):
Base address of the AHB device memory space. Taken
from Strap values as 1.s
11:4
00h
RO
Size Indicator Read Only (SIZEINDICATOR):
Always returns zero. The size of this
register depends on the size of the Memory space. This size is determined by a top level
of STRAP values as 0.s. Always will be zero as minimum size is 4K.
3
0h
RO
Prefetchable (PREFETCHABLE):
Indicates that this BAR is not prefetchable.