Intel E3845 FH8065301487715 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4263

The software controls the PWM block by updating the PWMCTRL register and setting the 
PWMCTRL.PWM_SW_UPDATE bit whenever a change in frequency or duty cycle of the 
PWM output signal is required. The PWM block applies the new settings at the start of 
the next output cycle and resets the PWMCTRL.PWM_SW_UPDATE bit. The SoC uses a 
25 MHz base clock rate for the PWM counter. See 

 for PWM block diagram:

There are two controls of the PWM output: 

•

Frequency is controlled by the PWMCTRL.PWM_BASE_UNIT register. The 
PWMCTRL.PWM_BASE_UNIT value is added to the 16 bit PWM counter every base 
clock cycle. The counter roll-over/overflow marks the start of a new cycle and 
resets the counter to the value in PWMCTRL.PWM_BASE_UNIT. 

•

Duty Cycle is controlled by the PWMCTRL.PWM_ON_TIME_DIVISOR setting (0 to 
255). When the 16 bit PWM counter is less than PWM_ON_TIME_DIVISOR * 256, 
the PWM output is low (0). When the 16 bit PWM counter is equal to or greater than 
PWM_ON_TIME_DIVISOR * 256, the PWM output is high (1).

The PWM block is clocked by the 25 MHz oscillator clock. The output frequency can be 
estimated with the equation: 

•

Target frequency = 25 MHz / CEILING(65536/PWM_BASE_UNIT) 
Note that the larger the value of base_unit, the larger the error that the PWM 
output frequency will have with respect to the equation above. For example any 
Base_unit_value/256 > 128 will result in 12.5 MHz max frequency. Any value 
between 86 and 128 will result in 8.33 MHz output frequency. And accordingly the 
larger the base_unit value the smaller duty cycle resolution. Maximum duty cycle 
resolution is 8 bits. 

 illustrates the output frequency and duty-cycle resolution for different 

settings of the base_unit_value (when using 25 MHz oscillator clock).

PWM Base Counter

A >= B

A 

B

Output

25 MHz 

Base Clock

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