Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
PCU – Power Management Controller (PMC)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4303
Power Button Override Function
If PMC_PWRBTN# is observed active for at least four consecutive seconds, the state
machine should unconditionally transition to the S5 state, regardless of present state
(S0–S4), even if the PMC_CORE_PWROK is not active. In this case, the transition to the
G2/S5 state should not depend on any particular response from the processor nor any
similar dependency from any other subsystem.
machine should unconditionally transition to the S5 state, regardless of present state
(S0–S4), even if the PMC_CORE_PWROK is not active. In this case, the transition to the
G2/S5 state should not depend on any particular response from the processor nor any
similar dependency from any other subsystem.
The PMC_ PWRBTN# status is readable to check if the button is currently being pressed
or has been released. The status is taken after the de-bounce, and is readable using
the GEN_PMCON2.PWRBTN_LVL bit.
or has been released. The status is taken after the de-bounce, and is readable using
the GEN_PMCON2.PWRBTN_LVL bit.
Note:
The 4-second PMC_PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the SoC is in a S0 state. If the
PMC_PWRBTN# signal is asserted and held active when the system is in a suspend
state (S3–S4), the assertion causes a wake event. Once the system has resumed to the
S0 state, the 4-second timer starts.
occurred. The 4-second timer starts counting when the SoC is in a S0 state. If the
PMC_PWRBTN# signal is asserted and held active when the system is in a suspend
state (S3–S4), the assertion causes a wake event. Once the system has resumed to the
S0 state, the 4-second timer starts.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by GEN_PMCON1.S4ASE), the power button is not a wake event. As a
result, it is conceivable that the user will press and continue to hold the power button
waiting for the system to awake. Since a 4-second press of the power button is already
defined as an unconditional power down, the power button timer will be forced to
inactive while the power-cycle timer is in progress. Once the power-cycle timer has
expired, the power button awakes the system. Once the minimum PMC_SLP_S4#
power cycle expires, the power button must be pressed for another 4 to 5 seconds to
create the override condition to S5.
(if enabled by GEN_PMCON1.S4ASE), the power button is not a wake event. As a
result, it is conceivable that the user will press and continue to hold the power button
waiting for the system to awake. Since a 4-second press of the power button is already
defined as an unconditional power down, the power button timer will be forced to
inactive while the power-cycle timer is in progress. Once the power-cycle timer has
expired, the power button awakes the system. Once the minimum PMC_SLP_S4#
power cycle expires, the power button must be pressed for another 4 to 5 seconds to
create the override condition to S5.
Table 289. Transitions Due to Power Button
Present
State
Event
Transition/Action
Comment
S0/Cx
PMC_PWRBTN# goes
low
low
SCI generated (depending on
PM1_CNT.SCI_EN and
PM1_STS_EN.PWRBTN_EN)
PM1_CNT.SCI_EN and
PM1_STS_EN.PWRBTN_EN)
Software typically initiates a
Sleep state
Sleep state
S3–S4/
S5
PMC_PWRBTN# goes
low
low
Wake Event. Transitions to S0
state
state
Standard wakeup
G3
PMC_PWRBTN#
pressed
pressed
None
No effect since no power
Not latched nor detected
Not latched nor detected
S0,
S3–S4
PMC_PWRBTN# held
low for at least 4
consecutive seconds
low for at least 4
consecutive seconds
Unconditional transition to S5
state
state
No dependence on processor
or any other subsystem
or any other subsystem