Intel E3845 FH8065301487715 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4413

BIOS control register. This register formerly was in the 0:31:0 config space

Default: 00000020h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
SPI_BASE_ADDRESS Reference: 

[B:0, D:31, F:0] + 54h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

RSV

D

0

EIS

S

RSV

D

1

SRC

LE

WPD

31:6

0b

RO

Reserved

5

1b

RW/L

When this bit is set, the BIOS region is writable only to 

SMM code. Today BIOS Flash is writable if WPD is a '1'. If this bit [lb]5[rb] is set, then 

WPD must be a 1'b1 and iosfep_xxx_hprot[lb]1[rb] signal be 1'b1 also. If this bit 

[lb]5[rb] is clear, then BIOS is writable based only on WPD = 1'b1 and the 

iosfep_xxx_hprot[lb]1[rb] signal is a don't care.

4

0b

RO

Reserved

3:2

00b

RW

This 2-bit field controls two policies related to BIOS 

reads on the SPI interface: Bit 3 - Prefetch Enable, Bit 2 - Cache Disable. Settings are 

summarized below: '00' : No prefetching, but caching enabled. Direct Memory reads 

load the read buffer cache with 'valid' data, allowing repeated reads to the same range 

to complete quickly. '01' : No prefetching and no caching. One-to-one correspondence 

of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. '10' : 

Prefetching and Caching enabled. This mode is used for long sequences of short reads to 

consecutive addresses (i.e. shadowing) '11' : Illegal. Caching must be enabled when 

Prefetching is enabled. This eliminates the need for a complex prefetch-flushing 

mechanism. Note that if BIOS direct read caching is disabled while data has already 

been cached internally, subsequent BIOS direct reads will continue to return data from 

the cache until the cache is invalidated.

1

0b

RW/L

When set, WPD bit could be set from a 1'b0 to a 1'b1 only by SMM 

code. When cleared, setting the WP bit is allowed in all modes and SMI is not generated. 

Once set, this bit can only be cleared by a PLTRST#. When this bit is set, EISS - bit 

[lb]5[rb] of this register is locked down.

0

0b

RW

When set, access to the BIOS space is enabled for both 

read and write cycles. When cleared, only read cycles are permitted to the flash. When 

LE bit is set this bit could be written from a 1'b0 to a 1'b1 only by SMM code. When not 

SMM code tries to writes this bit from a 1'b0 to a 1'b1, bit remain in its 1'b0 value. An 

Async-SMI is generated (Send ASSERT_SMI) if SMIWPEN is set. This ensures that only 

SMM code can update BIOS.