Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4451
33.6.21
D31_F3_PMCSR_BSE (SMB_Config_PMCSR_BSE)—Offset 56h
PMCSR_BSE supports PCI bridge specific functionality and is required for all PCI-to-PCI
bridges.
Access Method
Default: 00h
3
1b
RO
No_Soft_Reset (DSI):
When set (1), this bit indicates that devices transitioning from
D3hot to D0 because of PowerState commands do not perform an internal reset.
Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized
state, no additional operating system intervention is required to preserve Configuration
Context beyond writing the PowerState bits.
2
0b
RO
Reserved (RSV2):
Reserved
1:0
00b
RW
PowerState (PS):
This 2-bit field is used both to determine the current power state of
a function and to set the function into a new power state. The definition of the field
values is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to
write an unsupported, optional state to this field, the write operation must complete
normally on the bus; however, the data is discarded and no state change occurs.
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 8 bits)
SMB_Config_PMCSR_BSE:
7
4
0
0
0
0
0
0
0
0
0
BPCC
E
B23
RSV
1
Bit
Range
Default &
Access
Description
7
0b
RO
BPCC_En (BPCCE):
Bus Power/Clock Control Enable - Does not apply
6
0b
RO
B2_B3 (B23):
B2/B3 support for D3hot - Does not apply
5:0
00h
RO
Reserved (RSV1):
Reserved