Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
PCU – iLB – Low Pin Count (LPC) Bridge
Intel
®
Atom™ Processor E3800 Product Family
4518
Datasheet
35.2.4
Other Notes
All cycles that are not decoded internally, and are not targeted for LPC (i.e.
configuration cycles and IO cycles above 64kb) will be sent to LPC with
ILB_LPC_FRAME# not asserted. Memory cycles above 16 MB that are not decoded
internally, and are not targeted for LPC will be sent to LPC with ILB_LPC_FRAME#
asserted.
configuration cycles and IO cycles above 64kb) will be sent to LPC with
ILB_LPC_FRAME# not asserted. Memory cycles above 16 MB that are not decoded
internally, and are not targeted for LPC will be sent to LPC with ILB_LPC_FRAME#
asserted.
35.2.5
POST Code Redirection
Writes to addresses 80h - 8Fh in IO register space will also be passed to the LPC bus.
Note:
Reads of these addresses do not result in any LPC transactions.
35.2.6
Power Management
35.2.6.1
LPCPD# Protocol
Same timings as for PMC_SUS_STAT#. After driving PMC_SUS_STAT# active, the SoC
drives ILB_LPC_FRAME# low, and tri-states (or drives low) ILB_LPC_AD[3:0].
drives ILB_LPC_FRAME# low, and tri-states (or drives low) ILB_LPC_AD[3:0].
Note:
The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. The SoC asserts both
PMC_SUS_STAT# (connects to LPCPD#) and ILB_PLTRST# (connects to LRST#) at the
same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. The SoC asserts both
PMC_SUS_STAT# (connects to LPCPD#) and ILB_PLTRST# (connects to LRST#) at the
same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
35.2.6.2
Clock Run (CLKRUN)
When there are no pending LPC cycles, and SERIRQ is in quiet mode, the SoC can shut
down the LPC clock. The SoC indicates that the LPC clock is going to shut down by de-
asserting the ILB_LPC_CLKRUN# signal. LPC devices that require the clock to stay
running should drive ILB_LPC_CLKRUN# low within 4 clocks of its de-assertion. If no
device drives the signal low within 4 clocks, the LPC clock will stop. If a device asserts
ILB_LPC_CLKRUN#, the SoC will start the LPC clock and assert ILB_LPC_CLKRUN#.
down the LPC clock. The SoC indicates that the LPC clock is going to shut down by de-
asserting the ILB_LPC_CLKRUN# signal. LPC devices that require the clock to stay
running should drive ILB_LPC_CLKRUN# low within 4 clocks of its de-assertion. If no
device drives the signal low within 4 clocks, the LPC clock will stop. If a device asserts
ILB_LPC_CLKRUN#, the SoC will start the LPC clock and assert ILB_LPC_CLKRUN#.
Note:
The CLKRUN protocol is disabled by default. See
for further details.