Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
4560
Datasheet
37.6.8
NSC—Offset 61h
NMI Status and Control
Access Method
Default: 20h
Bit
Range
Default &
Access
Description
7:0
X
RW
CP:
Counter Port: Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
Type:
I/O Register
(Size: 8 bits)
NSC:
7
4
0
0
0
1
0
0
0
0
0
SNS
INS
T2S
RT
S
INE
SNE
SD
E
TC
2
E
Bit
Range
Default &
Access
Description
7
0b
RO
SNS:
SERR# NMI Status (SNS): Set on errors from a PCIe port or internal functions that
generate SERR#. SNE in this register must be cleared in order for this bit to be set. To
reset the interrupt, set bit 2 to 1 and then set it to 0.
6
0b
RO
INS:
IOCHK NMI Status (INS): Set when SERIRQ asserts IOCHK# and INE in this
register is cleared. To reset the interrupt, set bit 3 to 1 and then set it to 0.
5
1b
RO
RTS (T2S):
Timer Counter 2 Status (T2S): Reflects the current state of the 8254
counter 2 outputs. Counter 2 must be programmed for this bit to have a determinate
value.
4
0b
RO
RTS:
Refresh Cycle Toggle Status (RTS): Reflects the current state of 8254 counter 1
3
X
RW
INE:
IOCHK NMI Enable (INE): When set, IOCHK# NMIs are disabled. When cleared,
IOCHK# NMIs are enabled.
2
0b
RW
SNE:
SERR# NMI Enable (SNE): When set, SERR# NMIs are disabled. When cleared,
SERR# NMIs are enabled.
1
0b
RW
SDE:
Speaker Data Enable (SDE): When this bit is a 0, the SPKR output is a 0. When
this bit is a 1, the SPKR output is equivalent to the Counter 2 OUT signal value.
0
0b
RW
TC2E:
Timer Counter 2 Enable (TC2E): When cleared, counter 2 counting is disabled.
When set, counting is enabled.