Intel E3845 FH8065301487715 Data Sheet

Product codes
FH8065301487715
Page of 5308
 
PCU – iLB – GPIO
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
4573
39.3
Legacy Use
Each GPIO has six registers that control how it is used, or report its status:
Use Select
I/O Select
GPIO Level
Trigger Positive Edge
Trigger Negative Edge
Trigger Status
The Use Select register selects a GPIO pin as a GPIO, or leaves it as its programmed 
function. This register must be set for all other registers to affect the GPIO.
The I/O Select register determines the direction of the GPIO.
The Trigger Positive Edge and Trigger Negative Edge registers enable general purpose 
events on a rising and falling edge respectively. This only applies to GPIOs set as input. 
The Trigger Status register is used by software to determine if the GPIO triggered a 
GPE. This only applies to GPIOs set as input and with one or both of the Trigger modes 
enabled.
Additionally, there is one additional register for each S5 GPIO:
Wake Enable
This register allows S5 GPIOs to trigger a wake event based on the Trigger registers’ 
settings.
39.4
Memory Mapped Use
Each GPIO has two registers that control how it is used, or report its status:
- Pad Configuration (PCONF0)
- Pad Value (PAD_VAL)
Note: These registers are also implemented for the available Virtual GPIOs (vGPIOs).
The Pad Configuration register has the following functions:
- Configure the function of the pin as a GPIO or mulitplexed native functions
- Configure pull resistors
- Configure electrical behaviour
- Configure edge detection
- Configure interrupt handling
Note: The PCONF0 register is valid irrespective of whether or not the pin is conifgured as