Intel E3845 FH8065301487715 Data Sheet

Intel

Product codes

FH8065301487715

Intel

®

Atom™ Processor E3800 Product Family

5060

Datasheet

A0–A3h

4

“Pmu Wake Lan B Pad Configuration

(cfio_regs_pad_pmu_wake_lan_b_PCONF0)—Offset A0h” on page 5100

2003CC80h

A8–ABh

4

“Pmu Wake Lan B Pad Value (cfio_regs_pad_pmu_wake_lan_b_PAD_VAL)—

Offset A8h” on page 5103

00000002h

AC–AFh

4

“Pmu Wake Lan B Pad Test (cfio_regs_pad_pmu_wake_lan_b_PAD_DFT)—

Offset ACh” on page 5103

00000400h

B0–B3h

4

“Pmu Susclk Pad Configuration (cfio_regs_pad_pmu_susclk_PCONF0)—Offset

B0h” on page 5104

2003CD00h

B8–BBh

4

“Pmu Susclk Pad Value (cfio_regs_pad_pmu_susclk_PAD_VAL)—Offset B8h” on

00000002h

BC–BFh

4

“Pmu Susclk Pad Test (cfio_regs_pad_pmu_susclk_PAD_DFT)—Offset BCh” on

00000400h

C0–C3h

4

“Usb Oc0 B Pad Configuration (cfio_regs_pad_usb_oc0_b_PCONF0)—Offset

C0h” on page 5109

2003CC80h

C8–CBh

4

“Usb Oc0 B Pad Value (cfio_regs_pad_usb_oc0_b_PAD_VAL)—Offset C8h” on

00000002h

D0–D3h

4

“Pmu Slp S3 B Pad Configuration (cfio_regs_pad_pmu_slp_s3_b_PCONF0)—

Offset D0h” on page 5112

2003C800h

D8–DBh

4

“Pmu Slp S3 B Pad Value (cfio_regs_pad_pmu_slp_s3_b_PAD_VAL)—Offset

D8h” on page 5114

00000002h

DC–DFh

4

“Pmu Slp S3 B Pad Test (cfio_regs_pad_pmu_slp_s3_b_PAD_DFT)—Offset DCh”

00000400h

E0–E3h

4

“Pmu Ac Present Pad Configuration

(cfio_regs_pad_pmu_ac_present_PCONF0)—Offset E0h” on page 5116

2003CD00h

E8–EBh

4

“Pmu Ac Present Pad Value (cfio_regs_pad_pmu_ac_present_PAD_VAL)—Offset

E8h” on page 5119

00000006h

EC–EFh

4

“Pmu Ac Present Pad Test (cfio_regs_pad_pmu_ac_present_PAD_DFT)—Offset

ECh” on page 5119

00000400h

F0–F3h

4

“Pmu Slp S4 B Pad Configuration (cfio_regs_pad_pmu_slp_s4_b_PCONF0)—

Offset F0h” on page 5120

2003C800h

F8–FBh

4

“Pmu Slp S4 B Pad Value (cfio_regs_pad_pmu_slp_s4_b_PAD_VAL)—Offset

F8h” on page 5123

00000002h

FC–FFh

4

“Pmu Slp S4 B Pad Test (cfio_regs_pad_pmu_slp_s4_b_PAD_DFT)—Offset FCh”

00000400h

100–103h

4

“Pmu Pltrst B Pad Configuration (cfio_regs_pad_pmu_pltrst_b_PCONF0)—Offset

100h” on page 5124

2003C800h

108–10Bh

4

“Pmu Pltrst B Pad Value (cfio_regs_pad_pmu_pltrst_b_PAD_VAL)—Offset 108h”

00000002h

10C–10Fh

4

“Pmu Pltrst B Pad Test (cfio_regs_pad_pmu_pltrst_b_PAD_DFT)—Offset 10Ch”

00000400h

110–113h

4

“Pmu Slp Lan B Pad Configuration (cfio_regs_pad_pmu_slp_lan_b_PCONF0)—

Offset 110h” on page 5129

2003CC80h

118–11Bh

4

“Pmu Slp Lan B Pad Value (cfio_regs_pad_pmu_slp_lan_b_PAD_VAL)—Offset

118h” on page 5131

00000002h

11C–11Fh

4

“Pmu Slp Lan B Pad Test (cfio_regs_pad_pmu_slp_lan_b_PAD_DFT)—Offset

11Ch” on page 5132

00000400h

120–123h

4

“Sec Gpio Sus10 Pad Configuration (cfio_regs_pad_sec_gpio_sus10_PCONF0)—

Offset 120h” on page 5133

2003CC80h

Table 340.

Summary of iLB GPIO S5 Memory Mapped I/O Registers—IOBASE + 0x2000

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value