Intel E3845 FH8065301487715 Data Sheet
Product codes
FH8065301487715
SIO – Serial Peripheral Interface (SPI)
Intel
®
Atom™ Processor E3800 Product Family
3790
Datasheet
•
In a single frame transfer, the SPI controller supports all four possible combinations
for the serial clock phase and polarity.
for the serial clock phase and polarity.
25.2.2
Mode Numbers
The combinations of polarity and phases are referred to as modes which are commonly
numbered according to the following convention, with SSCR1.SPO as the high order bit
and SSCR1.SPH as the low order bit.
numbered according to the following convention, with SSCR1.SPO as the high order bit
and SSCR1.SPH as the low order bit.
25.2.3
Frame Direction
The SSCR1.SFRMDIR bit is a read-write bit that determines whether the SSP is the
master or slave with respect to driving the SSPSFRM. When SSCR1.SFRMDIR=0, the
SSP generates the SSPSFRM internally, acts as the master and drives it. When
SSCR1.SFRMDIR=1, the SSP acts as the slave and receives the SSPSFRM signal from
an external device. When the SSP is to be configured as a slave to the frame, the
external device driving frame must wait until the SSSR.CSS bit is cleared after enabling
the SSP before asserting frame (i.e. not external clock cycles are needed, the external
device just needs to wait a certain amount of time before asserting frame). When the
GPIO alternate function is selected for the SSP, this bit has precedence over the GPIO
direction bit (i.e. if SFRMDIR=1, the GPIO is an input, and if SFRMDIR=0, then the pin
is an output). Therefore, the SCLKDIR and SFRMDIR bits should be written to before
master or slave with respect to driving the SSPSFRM. When SSCR1.SFRMDIR=0, the
SSP generates the SSPSFRM internally, acts as the master and drives it. When
SSCR1.SFRMDIR=1, the SSP acts as the slave and receives the SSPSFRM signal from
an external device. When the SSP is to be configured as a slave to the frame, the
external device driving frame must wait until the SSSR.CSS bit is cleared after enabling
the SSP before asserting frame (i.e. not external clock cycles are needed, the external
device just needs to wait a certain amount of time before asserting frame). When the
GPIO alternate function is selected for the SSP, this bit has precedence over the GPIO
direction bit (i.e. if SFRMDIR=1, the GPIO is an input, and if SFRMDIR=0, then the pin
is an output). Therefore, the SCLKDIR and SFRMDIR bits should be written to before
Figure 118.Clock Phase and Polarity
D0
Data out
D1
D2
CLK
SSCR1.SPO=0
SS#
D3
D4
D5
D6
D7
Data in
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Data out
Data in
SSCR1.SPO=1
CLK
SSCR1.SPH=0
SSCR1.SPH=1
Table 254. SPI Modes
Mode
SSCR1
.
SPO SSCR1.SPH
0
0
0
1
0
1
2
1
0
3
1
1