Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1003
14.11.341 SPDLINOFF—Offset 72484h
Sprite D Linear Offset Register
Access Method
Default: 00000000h
0
0b
RW
SPRITE_D_Z_ORDER:
With Sprite C and D z-order, bottom control bits, Sprite D plane
is placed in a specific z-order among other planes in pipe B.
Display Pipe B Z-orders
SC
zorderSC
bottomSD
zorderSD
bottomResulting Pipe Z-order (from bottom to top)Source Keying
0000PB SC SD CBPB in Black
1000PB SD SC CBPB in Black
0001SD PB SC CBuse src keying on SD
0011SD PB SC CBuse src keying on SD
1001SD SC PB CBuse src keying on SC
1011SD SC PB CBuse src keying on SC
0100SC PB SD CBuse src keying on SC
1100SC PB SD CBuse src keying on SC
0110SC SD PB CBuse src keying on SD
1110SC SD PB CBuse src keying on SD
0101Not Allowed
0111Not Allowed
1101Not Allowed
1111Not Allowed
1010Not Allowed
1011Not Allowed
0: Sprite D z-order is disabled
1: Sprite D z-order is enabled
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE
_D_OFFSE
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0b
RW
SPRITE_D_OFFSET:
This register provides the panning offset into the Sprite D plane.
This value is added to the surface address to get the graphics address of the first pixel
to be displayed. This offset must be at least pixel aligned. This offset is the difference
between the address of the upper left pixel to be displayed and the display surface
address. When performing 180 rotation, this offset must be the difference between the
last pixel of the last line of the display data in its unrotated orientation and the display
surface address.