Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2293
18.7.158 Battery Charge (BATTERY_CHARGE_REG)—Offset 80E4h
Access Method
13
1b
RW
Enable Filter TX Idle (EN_FILT_TX_IDLE):
When set to 1 enables a filter function to
TX electrical idle signal at PCie PIPE. We have a filter that will set TXelecidle signal of
PCIe PIPE to 1 whenever we are in isolation state or power down transition states.
Power Well:
SUS
12
1b
RW
Enable Host Engine Generate PME (EN_HE_GEN_PME):
This is a global switch to
enable or not enable the host engine to generate a PME message.
Power Well:
SUS
11
1b
RW
Enable Isolation (EN_ISOL):
When set to '1' enable isolation
Power Well:
SUS
10
1b
RW
Enable L1 Caused P2 Overwrite (EN_L1_P2_OVR):
Set 1 to enable a new feature.
This new feature is designed to use L1 as a state to identify whether we should do P2
Overwrite or not. We used to use P1 state to identify whether or not to invoke P2
overwrite function.
Power Well:
SUS
9
0b
RW
Enable Core Clock Gating (EN_CORE_CG):
When set to '1' enable core clock gating
based on low power state entered
Power Well:
SUS
8
0b
RW
Enable PHY Status Timeout (EN_PHY_STS_TO):
When set to '1' enable PHY status
timeout function which is designed to cover the PCIePHY issue that we may have not
able to detect the PHY status toggle.
Power Well:
SUS
7
1b
RW
Ignore aux_pm_en PCIe Core (IGN_APE_PC):
When set to '1' ignore the
aux_pm_en reg from PCIe core to continue the remote wake/clock switching support
Power Well:
SUS
6
0b
RW
Enable P2 Overwrite P1 (EN_P2_OVR_P1):
When set to '1' enable P2 overwrite P1
when PCIe core has indicated the transition from P0 to P1. This is to enable entering the
even lower power state.
Power Well:
SUS
5
1b
RW
Enable P2 Remote Wake (EN_P2_REM_WAKE):
When set 1 '1' enable the remote
wake function by allowing P2 clock/switching and P2 entering
Power Well:
SUS
4:1
0h
RW
Forced PM State (FORCED_PM_STATE):
Reserved.
Power Well:
SUS
0
0b
RW
Initiate Force PM State (INIT_FPMS):
When set to '1' force PM state to go to the
state indicated in bit 4:1
Power Well:
SUS
Bit
Range
Default &
Access
Field Name (ID): Description