Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2344
Datasheet
17:14
0h
RO
Reserved (RSVD_1):
Reserved.
Power Well:
Core
13
0b
RW
Enable ACK FIFO ICA mechanisms (EN_ACK_FIFO_ICA):
Setting this field will
enable ACK FIFO individual credit accounting mechanisms for Async vs. Periodic
Endpoints. ODMA will ensure that ample room exists in the ACK FIFO for expected
device responses prior to initiating a given DP
Power Well:
Core
12:9
0h
RO
Reserved (RSVD_2):
Reserved.
Power Well:
Core
8
0b
RW
Clear ownership of context semaphore (CL_OWN_CS):
Setting this field generates
a pulse that clears the ownership of the context semaphore that is shared between the
Out DMA Response and Completion Finite State Machines
Power Well:
Core
7
0b
RW
Return OD ACK credits (RET_OD_ACK_CR):
Setting this field generates a pulse that
implicitly returns all of the Out DMA ACK credits on all ports
Power Well:
Core
6
0b
RO
Reserved (RSVD_3):
Reserved.
Power Well:
Core
5
0b
RW
Return ODCF SM to idle state (RET_ODCF_SM_IS):
Setting this field generates a
pulse that returns the Out DMA Completion Finite State Machine into the IDLE state
Power Well:
Core
4
0b
RW
Return ODRF SM to idle state (RET_ODRF_SM_IS):
Setting this field generates a
pulse that returns the Out DMA Response Finite State Machine into the IDLE state
Power Well:
Core
3
0b
RW
Return ODRDF SM to idle state (RET_ODRDF_SM_IS):
Setting this field generates
a pulse that returns the Out DMA Read Finite State Machine into the IDLE state
Power Well:
Core
2:0
0h
RO
Reserved (RSVD_4):
Reserved.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description