Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2808
Datasheet
21.6
SSP (I
2
S)
The SoC audio subsystem consists of the LPE Audio Engine and three Synchronous
Serial Protocol (SSP) ports. These ports are used in PCM mode and enable
simultaneous support of voice and audio streams over I
Serial Protocol (SSP) ports. These ports are used in PCM mode and enable
simultaneous support of voice and audio streams over I
2
S. The SoC audio subsystem
also includes two DMA controllers dedicated to the LPE. The LPE DMA controllers are
used for transferring data between external memory and CCMs, between CCMs and the
SSP ports, and between CCMs. All peripheral ports can operate simultaneously.
used for transferring data between external memory and CCMs, between CCMs and the
SSP ports, and between CCMs. All peripheral ports can operate simultaneously.
21.6.1
Introduction
The Enhanced SSP Serial Ports are full-duplex synchronous serial interfaces. They can
connect to a variety of external analog-to-digital (A/D) converters, audio, and
telecommunication codecs, and many other devices which use serial protocols for
transferring data. Formats supported include National* Microwire, Texas Instruments*
Synchronous Serial Protocol (SSP), Motorola* Serial Peripheral Interface (SPI) protocol
and a flexible Programmable Serial Port protocol (PSP).
connect to a variety of external analog-to-digital (A/D) converters, audio, and
telecommunication codecs, and many other devices which use serial protocols for
transferring data. Formats supported include National* Microwire, Texas Instruments*
Synchronous Serial Protocol (SSP), Motorola* Serial Peripheral Interface (SPI) protocol
and a flexible Programmable Serial Port protocol (PSP).
The Enhanced SSPs operate in master mode (the attached peripheral functions as a
slave) or slave mode (the attached peripheral functions as a master), and support
serial bit rates from 0 to 25 Mbps, dependent on the input clock. Serial data formats
range from 4 to 32-bits in length. Two on-chip register blocks function as independent
FIFOs for transmit and receive data.
slave) or slave mode (the attached peripheral functions as a master), and support
serial bit rates from 0 to 25 Mbps, dependent on the input clock. Serial data formats
range from 4 to 32-bits in length. Two on-chip register blocks function as independent
FIFOs for transmit and receive data.
FIFOs may be loaded or emptied by the system processor using single transfers or DMA
burst transfers of up to the FIFO depth. Each 32-bit word from the bus fills one entry in
a FIFO using the lower significant bits of a 32-bit word.
burst transfers of up to the FIFO depth. Each 32-bit word from the bus fills one entry in
a FIFO using the lower significant bits of a 32-bit word.
21.6.2
SSP Features
The SSP port features are:
•
Inter-IC Sound (I
2
S) protocols, are supported by programming the Programmable
Serial Protocol (PSP).
•
One FIFO for transmit data (TXFIFO) and a second, independent, FIFO for receive
data (RXFIFO), where each FIFO is 16 samples deep x 32 bits wide
data (RXFIFO), where each FIFO is 16 samples deep x 32 bits wide
•
Data sample sizes from 8, 16, 18 and 24bits
Table 227. M/N Configurable Fields
Field
Width
Description
Bypass
1 bit
When set M/N divider is bypass. Clock from CCU is connected directly to
SSP CCLK
SSP CCLK
EN
1 bit
Enable the divider
Update
1 bit
Update divider parameters
M Value
20 bits
Nominator value
N Value
20 bits
Denominator value