Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2871
21.12.7
SSP Programmable Protocol Register (SSPSP)—Offset 2Ch
The Enhanced SSP Programmable Protocol registers are read-write registers that
contain eight fields that are used to program the various programmable serial-protocol
parameters. When using PSP format in Network mode, the parameters SFRMDLY,
STRTDLY, DMYSTP, DMYSTRT must be set to 0. Other parameters (such as FRMPOL,
SCMODE, FSRT, SFRMDWDTH) are programmable. Note that Writes to reserved bits
must be zeroes, and Read value of these bits are undetermined.
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Description
31:24
00h
RO
RSVD:
Reserved
23:0
000000h
RW
Timeout Value (TIMEOUT):
Is the value that defines the timeout interval, given by
TIMEOUT/Peripheral Clock Frequency
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSPSP:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD1
FSR
T
DMY
S
TO
P
RS
VD2
SF
R
M
W
D
T
H
SFRMDL
Y
DM
YS
T
R
T
ST
R
T
DL
Y
ETD
S
SFRMP
SC
MO
DE
Bit
Range
Default &
Access
Description
31:26
000000b
RO
RSVD1:
Reserved
25
0b
RW
Frame Sync Relative Timing Bit (FSRT):
0 = Next frame is asserted after the end of
the T4 timing 1 = Next frame is asserted with the LSB of the previous frame
24:23
00b
RW
Dummy Stop (DMYSTOP):
Programmed value sets the number of SSPSCLK cycles
that follow the transmitted data
22
0b
RW
RSVD2:
Reserved
21:16
000000b
RW
Serial Frame Width (SFRMWDTH):
Programmed value sets frame width (1-38)
15:9
0000000b
RW
Serial Frame Delay (SFRMDLY):
Programmed value sets the number of half SSPSCLK
cycles from TXD/RXD being driven to SSPSFRM being asserted (0-74)
8:7
00b
RW
Dummy Start (DMYSTRT):
Programmed value sets the number of SSPSCLKs after
STRTDLY is complete that precede the transmit/receive data
6:4
000b
RW
Start Delay (STRTDLY):
Programmed value sets start delay that is used to set the idle
time of SSPSCLK between transfers (0-7 SSPSCLK periods)
3
0b
RW
End of Transfer Data State (ETDS):
0 = Low 1 = Last value (bit 0)