Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2927
21.15.1
reg_SAR_type (SAR0)—Offset 0h
The starting source address is programmed by software before the DMA channel is
enabled, or by an LLI update before the start of the DMA transfer. While the DMA
transfer is in progress, this register is updated to reflect the source address of the
current transfer.
Access Method
Default: 00000000h
2F8h
4
00000000h
300h
4
00000000h
308h
4
00000000h
310h
4
00000000h
318h
4
00000000h
320h
4
00000000h
328h
4
00000000h
330h
4
00000000h
338h
4
00000000h
340h
4
00000000h
348h
4
00000000h
350h
4
00000000h
358h
4
00000000h
360h
4
00000000h
398h
4
00000000h
3A0h
4
00000000h
3B8h
4
00000000h
3BCh
4
00000000h
3C0h
4
00000000h
3C4h
4
00000000h
400h
4
00000000h
404h
4
00000000h
408h
4
00000000h
40Ch
4
00000000h
410h
4
00000000h
418h
4
00000000h
Table 235.
Summary of Low Power Audio DMA0 Memory Mapped I/O Registers—
lpe_bridge.BAR (Continued)
Offset
Size
Register ID—Description
Default
Value
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SAR0:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h