Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

30

Datasheet

All features subject to software availability.

See 

Chapter 3, “Processor Core”

 for more details.

•

Up to four IA-compatible low power Intel

®

 processor cores

— One thread per core

•

Two-wide instruction decode, out of order execution

•

On-die, 32 KB 8-way L1 instruction cache and 24 KB 6-way L1 data cache per core

•

On-die, 1 MB, 16-way L2 cache, shared per two cores

•

L1 has parity protection and L2 has ECC protection

•

36-bit physical address, 48-bit linear address size support

•

Supported C-states: C0, C1, C6

•

Supports Intel

®

 Virtualization Technology (Intel

®

 VT-x)

See 

Chapter 4, “System Memory Controller”

 for more details.

•

Supports up to two channels of DDR3L

•

64 bit data bus for each channel

•

ECC supported in single channel mode only

•

 Supports x8 and x16 DDR3L SDRAM device data widths

•

Supports DDR3L with 1066 or 1333 MT/s data rates

— Total memory bandwidth supported is 8.5 GB/s (for 1066 MT/s single channel) 

scalable to 21.3GB/s(for 1333 MT/s dual channel)

•

Supports different physical mappings of bank addresses to optimize performance

SMI

System Management Interrupt is used to indicate any of several system conditions 
(such as thermal sensor events, throttling activated, access to System 
Management RAM, chassis open, or other system state related activity).

SIO

Serial I/O

TMDS

Transition-Minimized Differential Signaling. TMDS is a serial signaling interface 
used in DVI and HDMI to send visual data to a display. TMDS is based on low-
voltage differential signaling with 8/10b encoding for DC balancing.

VCO

Voltage Controlled Oscillator

Warm 
Reset

Host Reset without Power Cycle. See