Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3155
22.3.3
Revision ID and Class Code (REVCLASSCODE)—Offset 8h
Revision ID and Class Code. Register acces control: FW=RO PMC=RW Host=RW
Access Method
Default: 10800000h
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
NA
RESERVED (RSVD_31_31):
RESERVED BITS
30
X
RW/C
SIGNALED_SYSTEM_ERROR_30:
SERR status, write 1 to clear.
29
X
RW/C
RMA:
SERR status, write 1 to clear.
28:21
0b
NA
RESERVED (RSVD_28_21):
RESERVED BITS
20
1b
RO
CAPLIST:
CAP: Indicates that the CAPPOINT register at 34h provides an offset into PCI
Configuration Space containing a pointer to the location of the first item in the list
19
X
RO
INTR_STATUS:
IS: Reflects the state of the interrupt in the graphics device. Is set to 1
if interrupt (as determined by IIR and IER memory interface registers) is set to 1.
Otherwise is set to 0
18:11
0b
NA
RESERVED (RSVD_18_11):
RESERVED BITS
10
X
RW
INTR_DISABLE:
ID: When 1, blocks the sending of a MSI interrupt and blocks the
sending of a Message bus interrupt. The interrupt status is not blocked from being
reflected in COMMANDSTATUS. INTR_STT. When 0, permits the sending of a MSI
interrupt or Message bus interrupt. Note: Overall, a MSI interrupt is sent when the
expression (COMMANDSTATUS. INTR_STT and ~COMMANDSTATUS. INTR_DIS and
COMMANDSTATUS.BUS_MSTR_EN and MSI_CAPID.MSI_EN) changes from 0 to 1.
Overall, a Message bus interrupt assert is sent when the expression (COMMANDSTATUS.
INTR_STT and ~COMMANDSTATUS. INTR_DIS and ~MSI_CAPID.MSI_EN) changes from
0 to 1. The corresponding Message bus interrupt de-assert is sent when the expression
(COMMANDSTATUS. INTR_STT and ~COMMANDSTATUS. INTR_DIS and
~MSI_CAPID.MSI_EN) changes from 1 to 0
9
0b
NA
RESERVED (RSVD_9_9):
RESERVED BITS
8
X
RW
INTR_STATUS (SERR_EN_8):
SERR enable.
7:3
0b
NA
RESERVED (RSVD_7_3):
RESERVED BITS
2
X
RW
BME:
BME: Enables GVD to function as a PCI compliant master. When 0, blocks the
sending of MSI interrupts and DDR transactions. When 1, permits the sending of MSI
interrupts and DDR transactions. Note: transactions to SEC paging IMR are not
controlled (enabled/disabled) by this field
1
X
RW
MSE:
MSE: When set, accesses to this device's memory space is enabled. When 1, SEC
will compare IOSF primary address MS bits with its BARs MS bits. If there is a match
and if the IOSF command is either a MEMRD or MEMWR, SEC send the command to the
destination pointed by the base address. Care should be taken in setting up SEC BARs
that more than 1 match is not made as this will result in unpredictable behavior. When
0, the SEC will not select a MEMRD or MEMWR IOSF command
0
0b
NA
RESERVED (RSVD_0_0):
IOSE: Since SEC doesn't have I/O space, this bit is hard
coded to 0. RESERVED BITS
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: