Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3181

— (2)  x2’s

— (1) x2 plus (2) x1’s

— (1)  x4

•

Interrupts and Events

— Legacy  (INTx) and MSI Interrupts

— General Purpose Events

— Express Card Hot Plug Events

— System Error Events

•

Power Management

— Link State support for L0s, L1 and L2

— Powered down in ACPI S3 state - L3

Depending on SKU, there are up to four possible lane assignments for root ports 1-4.

Root port configurations are set by SoftStraps stored in SPI flash, and the default 
option is “(4) x1”. Links for each root port will train automatically to the maximum 
possible for each port.

x2 link widths are not common. Most devices will only train to x1 or x4.

PCI functions in PCI configuration space are disabled for root ports not available.

PCIe* 2.0

RP 1

RP 2

RP 3

RP 4

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

Root Port 2

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

RP 2

RP 3

Lane 0 Lane 1 Lane 2 Lane 3

PCIe* 2.0

Root Port 1

Lane 0 Lane 1 Lane 2 Lane 3

(4) x1

(1) x2, (2) x1

(2) x2

(1) x4