Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3369
23.12.16 TX_DWORD15 (tx_dword15)—Offset 3Ch
Access Method
Default: 00000000h
26
0h
RW
ofrcdatapathen:
DFT feature to optionaly be used with other registers
25
0h
RW
ofrcdrvbypdis:
DFT feature to optionaly be used with other registers
24
0h
RW
ofrcdrvbypen:
DFT feature to optionaly be used with other registers
23
0h
RW
odfttxclkcaptesten:
Enables the finger capacitor quality check in the DCC block in Tx-
clock block. The test is for shorts between the capacitor terminals.
22
1h
RW
otxdccbyps_l:
Tx DCC Bypass Override Puts DCC (duty cycle correction) circuit in
bypass mode 0 - clock's duty cycle is not fixed
21:19
0h
RW
ofrcnmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
18:16
0h
RW
ofrcpmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
15
0h
RW
visa_en:
VISA Enable for the Tx VISA logic
14:12
0h
RW
ovisa1_clksel_2_0:
VISA Clock Select for Lane1. Selects the source synchronous
clock to be used for data being sent on lane1.
11:8
0h
RW
ovisa1_lanesel_3_0:
VISA Lane Select for Lane1. Selects the byte of data to be sent
out on lane1.
7
0h
RW
ovisa_bypass:
VISA Bypass. Allows for signals to be passed asynchronously through
VISA block. Applies to both lane0 and lane1. 0 : Flop signals in local VISA block
(default) 1 : Bypass flops in local VISA block
6:4
0h
RW
ovisa0_clksel_2_0:
VISA Clock Select for Lane0. Selects the source synchronous
clock to be used for data being sent on lane0.
3:0
0h
RW
ovisa0_lanesel_3_0:
VISA Lane Select for Lane0. Selects data byte to be driven out
of VISA-0 byte. Can be either clocked or unclocked data
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
tx_dword15:
[Port: 0xA6] + (680h + 3Ch)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
se
rv
ed
551
re
se
rv
ed
550
re
se
rv
ed
549
re
se
rv
ed
548
re
se
rv
ed
547
re
se
rv
ed
546
re
se
rv
ed
545
re
se
rv
ed
544