Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

3433

128–12Bh

4

“Source Status Register for Channel 3 - Low (SSTAT3_LO)—Offset 128h” on

00000000h

12C–12Fh

4

“Source Status Register for Channel 3 - High (SSTAT3_HI)—Offset 12Ch” on

00000000h

130–133h

4

“Dest Status Register for Channel 3 - Low (DSTAT3_LO)—Offset 130h” on

00000000h

134–137h

4

“Dest Status Register for Channel 3 - High (DSTAT3_HI)—Offset 134h” on

00000000h

138–13Bh

4

“Source Status Address Register for Channel 3 - Low (SSTATAR3_LO)—Offset

138h” on page 3485

00000000h

13C–13Fh

4

“Source Status Address Register for Channel 3 - High (SSTATAR3_HI)—Offset

13Ch” on page 3486

00000000h

140–143h

4

“Dest Status Address Register for Channel 3 - Low (DSTATAR3_LO)—Offset

140h” on page 3486

00000000h

144–147h

4

“Dest Status Address Register for Channel 3 - High (DSTATAR3_HI)—Offset

144h” on page 3487

00000000h

148–14Bh

4

“Configuration Register for Channel 3 - Low (CFG3_LO)—Offset 148h” on

00000E60h

14C–14Fh

4

“Configuration Register for Channel 3 - High (CFG3_HI)—Offset 14Ch” on

00000004h

150–153h

4

“Source Gather Register for Channel 3 - Low (SGR3_LO)—Offset 150h” on

00000000h

154–157h

4

“Source Gather Register for Channel 3 - High (SGR3_HI)—Offset 154h” on

00000000h

158–15Bh

4

“Destination Scatter Register for Channel 3 - Low (DSR3_LO)—Offset 158h” on

00000000h

15C–15Fh

4

“Dest Scatter Register for Channel 3 - High (DSR3_HI)—Offset 15Ch” on

00000000h

160–163h

4

“Source Address Register for Channel 4 - Low (SAR4_LO)—Offset 160h” on

00000000h

164–167h

4

“Source Address Register for Channel 4 - High (SAR4_HI)—Offset 164h” on

00000000h

168–16Bh

4

“Destination Address Register for Channel 4 - Low (DAR4_LO)—Offset 168h” on

00000000h

16C–16Fh

4

“Destination Address Register for Channel 4 - High (DAR4_HI)—Offset 16Ch” on

00000000h

170–173h

4

“Linked List Pointer Register for Channel 4 - Low (LLP4_LO)—Offset 170h” on

00000000h

174–177h

4

“Linked List Pointer Register for Channel 4 - High (LLP4_HI)—Offset 174h” on

00000000h

178–17Bh

4

“Control Register for Channel 4 - Low (CTL4_LO)—Offset 178h” on page 3494

00304801h

17C–17Fh

4

“Control Register for Channel 4 - High (CTL4_HI)—Offset 17Ch” on page 3495

00000002h

180–183h

4

“Source Status Register for Channel 4 - Low (SSTAT4_LO)—Offset 180h” on

00000000h

184–187h

4

“Source Status Register for Channel 4 - High (SSTAT4_HI)—Offset 184h” on

00000000h

188–18Bh

4

“Dest Status Register for Channel 4 - Low (DSTAT4_LO)—Offset 188h” on

00000000h

Table 251.

Summary of SIO DMA 1 Memory Mapped I/O Registers—BAR (Continued)

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value